Marching Orders


Reports back from the front lines of Moore’s Law are rather consistent—14nm and 16nm finFETs are do-able, but they’re not easy to design, verify or manufacture. In fact, the only high-volume source of production-proven finFETs at this point is Intel, which is turning them out at 22nm. A number of issues are cropping up at the most advanced nodes, and while each is ultimately solvable, ... » read more

Apple’s Big Breakthrough


By Cary Chin For literally years now, we’ve talked about and measured energy consumption as smartphones have morphed from primarily communications devices (voice), to the world’s most widespread computing platform, and back again to a communications focus. But this time it’s data communications, and voice calls are just a small subset. Smartphones themselves, once the defining standar... » read more

Scaling The Lowly SRAM


By Mark LaPedus Chipmakers face a multitude of challenges at the 20nm logic node and beyond, including the task of cramming more functions on the same chip without compromising on power and performance. There is one major challenge that is often overlooked in the equation—scaling the lowly static RAM (SRAM). In one key application, SRAM is the component used to make on-chip cache memories... » read more

Experience Required


Many prominent semiconductor, EDA and IP companies are acknowledging the influence of user-experience design methodologies and technologies on their business. Experiences are the evolution of commoditization (chip hardware) and customization (software). But many design engineers remain cautious about the actual application of experiences to their work. What is driving this emphasis on expe... » read more

The Bumpy Road To 450mm


By Mark LaPedus After its formation nearly 20 months ago, a 450mm consortium has reached its latest milestone by recently completing a cleanroom and installing the first 450mm demonstration tools in the facility. The so-called Global 450 Consortium (G450C) also has set a goal to bring 450mm fabs into high-volume manufacturing at the 10nm or 7nm nodes by 2018. That gives the industry a littl... » read more

Bigger Wafers, Bigger Risk


At 22/20/16/14nm the semiconductor industry is experiencing a rather new twist on Moore’s Law. Smaller, as in smaller feature sizes, is no longer assumed to be cheaper—or at least not for everyone. In fact, the cost per transistor for the first time in more than half a century could rise in some cases. Whether this outlook improves as the semiconductor industry gains more experience wit... » read more

Subsystems And Reuse


By Frank Schirrmeister The last couple of weeks have been very busy with travel, customer meetings and presentations—DATE in Grenoble, CDNLive in San Jose and, most recently, EDPS in Monterey. Software enablement and IP sub-systems have been the key themes throughout these events, and during Gary Smith’s keynote at EDPS, I realized that subsystem reuse may be a significant step to solving ... » read more

Design-For-DSA Industry Begins To Assemble


By Mark LaPedus The industry is aggressively pursuing directed self-assembly (DSA) as an alternative patterning technology for future chip designs. DSA, which enables fine pitches through the use of block copolymers, is in the R&D pilot line stage today. The fab tools, process flows and materials are basically ready, but there are still several challenges to bring the technology from th... » read more

Foundry Models In Transition


By Jeff Chappell There may have been a time when AMD founder Jerry Sanders famous quote: "real men (i.e., real companies) have their own fabs” rang true, but in today's business climate it seems quaint at best. Fabless or fab-lite business models are more popular than ever today, while some IDMs have turned back the clock, so to speak, looking to improve capacity utilization and revenues ... » read more

Waiting For 3D Metrology


By Mark LaPedus Over the years, suppliers of metrology equipment have managed to meet the requirements for conventional planar chips. But tool vendors now find themselves behind in the emerging 3D chip era, prompting the urgent need for a new class of 3D metrology gear. 3D is a catch-all phrase that includes a range of new architectures, such as finFET transistors, 3D NAND and stacked-die ... » read more

← Older posts Newer posts →