tag: IP

Week In Review: System-Level Design
By Ed Sperling - 17 Jan, 2014 - Comments: 0

Cadence rolled out a new version of its functional verification platform, greatly improving performance and updating it to deal with the big increases in third-party and re-used IP in designs. For IP and block verification, the company said it increased formal analysis performance by up to 20% and simulation by up to 10 times. The debugger also reduces the database size by 10 times and the time... » read more

Which IP Is Better?
By Ed Sperling - 16 Jan, 2014 - Comments: 0

As the amount of third-party and re-used IP in a semiconductor increases, so do the number of questions about which possible IP choices perform better, use the least power, or work best with other components. So far, there is no simple way to make that choice. In most cases, this is simply splitting hairs. For all the IP that goes into designs, the bulk of it is chosen based on how often has... » read more

Reducing Power Consumption in Mobile Applications with High-Speed Gear3 MIPI M-PHY IP
By Various Writers - 15 Jan, 2014 - Comments: 1

Mobile systems require increasing data volume for multiple chip-to-chip interfaces. The high-speed MIPI® M-PHY is tailored for mobile systems where performance, power, and efficiency are key criteria. With up to 5,824 Mbps bandwidth, the speed meets devices’ high bandwidth and scalability requirements. The M-PHY is designed to accommodate the intermittent nature of inter-chip communications ... » read more

The Integrated IP Subsystem: A Converging SoC Solution
By Various Writers - 15 Jan, 2014 - Comments: 0

The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a multitude of challenges when designing and developing ICs, systems, or subsystems for the next great portable device. The next cell phone for instance, will not only be a multimedia player, but also a ... » read more

Experts At The Table: Yield And Reliability Issues With Integrating IP
By Ed Sperling - 08 Jan, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of integrating IP in complex SoCs with Juan Rey, senior director of engineering at Mentor Graphics; Kevin Yee, product marketing director for Cadence’s SoC Realization Group; and Mike Gianfagna, vice president of marketing at eSilicon. What follows are excerpts of that conversation. SE: Do we need to move to subsystems or more restri... » read more

Tech Talk: FPGA Prototyping
By Ed Sperling - 03 Jan, 2014 - Comments: 0

Neil Songcuan, senior product marketing manager at Synopsys, examines the hidden time savings from using an FPGA prototype platform for IP validation and software development, in addition to hardware design. While FPGA prototypes are a well known way of speeding up hardware design, their value in IP validation and software development for an integrated SoC is just beginning to surface. [you... » read more

The End Is Near
By Ed Sperling - 30 Dec, 2013 - Comments: 0

Looking back is easier than looking forward, and looking narrow is easier than looking wide. In 2013, there were several fundamental changes. Change No. 1: IP is now a lucrative market. From Synopsys’ standpoint, it’s been a lucrative market for some time. But the acquisitions made by Cadence, beginning in late 2012, coupled with the push by ARM into the micro-server market and the flail... » read more

When Is Verification Done?
By Ed Sperling - 20 Dec, 2013 - Comments: 0

Verification is becoming much more difficult at 16nm/14nm, driven by the sheer complexity of SoCs, the fact that there is much more to verify, and the impact of physical effects, which now affect what used to be exclusively the realm of functional verification. The questions these changes raise are daunting, and for many engineers rather unnerving. The whole validation, verification and debu... » read more

Week In Review: System-Level Design
By Ed Sperling - 20 Dec, 2013 - Comments: 0

Synopsys extended its FPGA prototyping board with a new version that is optimized for IP and subsystems. This is particularly interesting given the fact that Synopsys is one of the largest IP providers and currently sells subsystems based on its ARC processor IP. Among the new features are support for 4 million gates for software development and hardware-software integration, as well as synthes... » read more

Where Is 2.5D?
By Ed Sperling - 19 Dec, 2013 - Comments: 3

After nearly five years of concentrated research, development, test chips and characterization, 2.5D remains a possibility for many companies but a reality for very few. So what’s taking so long and why hasn’t all of this hype turned into production runs instead of test chips? Semiconductor Engineering spent the past two months interviewing dozens of people on this subject, from chipmakers ... » read more

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