tag: Mentor Graphics

FinFET And Multi-Patterning Aware Place And Route Implementation
By Mentor, a Siemens Business - 21 May, 2014 - Comments: 0

The use of finFETs and multi-patterning has a huge impact on the entire physical implementation flow. This paper outlines the new challenges in placement, routing, optimization, and physical verification and describes how the Olympus-SoC place and route system handles them. To view this white paper, click here. » read more

Tech Talk: Silicon Photonics
By Ed Sperling - 21 May, 2014 - Comments: 2

Mentor Graphics' John Ferguson explains why light is getting so much attention for inter-chip communications, where it excels, and why it has limitations. This is the first part in a two-part series. [youtube vid=0ydkDmrSrF4] » read more

Blog Review: May 21
By Ed Sperling - 21 May, 2014 - Comments: 0

Mentor’s Colin Walls offers up some new insights into C++ exception handling, thanks to some input from colleague Jonathan Roelofs. This one involves minimizing overhead and reducing runtime penalties. Synopsys’ Mick Posner is back in the saddle again—literally. This is about as green as it gets. Cadence’s Arthur Marris reports back on the IEEE 802.3 Ethernet standards meeting, in... » read more

EDA Races To 7nm, Despite Litho Uncertainties
By Ann Mutschler - 16 May, 2014 - Comments: 0

It’s becoming almost painful to refer to the delay with EUV, but it certainly isn’t stopping anyone on the design side from tweaking design tools or working on test chips. Clearly, things are moving ahead to 7nm even though lithography plans aren't yet clear. Steve Carlson, group marketing director in Cadence’s Office of Chief Strategy, said with regard to EUV, “They have the power p... » read more

The Week In Review: Design
By Ed Sperling - 16 May, 2014 - Comments: 0

M&A Synopsys’ Coverity subsidiary bought Kalistick, a French company that makes cloud-based solutions to boost testing efficiency by allowing engineers to identify and prioritize tests. Terms of the deal were not disclosed. Tools Cadence rolled out verification IP for the new PCI Express 4.0 architecture. The new spec supports up to 16 billion transactions per second, which is double... » read more

How Much Testing Is Enough?
By Mark LaPedus - 15 May, 2014 - Comments: 1

As chipmakers move towards finer geometries, IC designs are obviously becoming more complex and expensive. Given the enormous risks involved, chipmakers must ensure the quality of the parts before they go out the door. And as part of quality assurance process, that requires a sound test strategy. But for years, IC makers have faced the same dilemma. On one hand, they want a stringent test me... » read more

Test Challenges Grow
By Mark LaPedus - 15 May, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss current and future test challenges with Dave Armstrong, director of business development at Advantest; Steve Pateras, product marketing director for Silicon Test Solutions at Mentor Graphics; Robert Ruiz, senior product marketing manager at Synopsys; Mike Slessor, president of FormFactor; and Dan Glotter, chief executive of Optimal+. SE: What are... » read more

Self-Aligned Double Patterning, Part One
By David Abercrombie - 15 May, 2014 - Comments: 0

I’m sure most of you have seen a Rorschach test ink blot (Figure 1). Psychiatrists ask the subjects to tell them what they “see” in the ink blot. The answers are used to characterize the respondent’s personality and emotional functioning. I am never sure if I would feel more uncertain being the psychiatrist asking the question, or the subject trying to decide what to say, given there ar... » read more

Blog Review: May 14
By Ed Sperling - 14 May, 2014 - Comments: 0

Ansys’ Bill Vandermark highlights the top five engineering articles of the week. Of particular note is element No. 117, a new entry in the periodic table. The temporary name is ununseptium, which means…well, surprise…117. Cadence’s Brian Fuller follows a panel discussion about the biggest potential roadblock for the IoT’s success—privacy and security. You’ve been warned. Syn... » read more

Divide And Conquer: Hierarchical DFT For SoC Designs
By Mentor, a Siemens Business - 14 May, 2014 - Comments: 0

Large System on Chip (SoC) designs present many challenges to all design disciplines, including design-for-test (DFT). By taking a divide-and-conquer approach to test, significant savings in tool runtime and memory consumption can be realized. This whitepaper describes the basic components of a hierarchical DFT methodology, the benefits that it provides, and the tool automation that is availabl... » read more

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