tag: Mentor

Blog Review: Sept. 25
By Jesse Allen - 25 Sep, 2019 - Comments: 0

Mentor's Dave Rich points out that unexpected values from a constraint solver can often be explained by how Verilog expression evaluation rules affect the solution space of SystemVerilog constraints. Cadence's Madhavi Rao points to the need for new and updated safety and cybersecurity standards for autonomous vehicles and highlights one of the most challenging parts of AV deployment. A Sy... » read more

Blog Review: Sept. 18
By Jesse Allen - 18 Sep, 2019 - Comments: 0

Cadence's Paul McLellan checks out MLPerf and the challenges involved in developing a benchmark to assess machine learning training and inference performance. Synopsys' Om Prakash Thakur and Nusrat Ali take a look at the different types of NVDIMM and how it can bridge the performance gap between memory and storage solutions in servers. Mentor's Matthew Ballance points to why adoption of P... » read more

EDA Revenue Up 6.6% For Q2
By Ann Mutschler - 17 Sep, 2019 - Comments: 0

Highlighted by double digit growth in semiconductor IP and the Asia/Pacific region, EDA industry revenue increased 6.6% for Q2 2019 to $2,472.1 million, compared to $2,318.5 million in Q2 2018, according to the ESD Alliance Market Statistics Service. The four-quarters moving average, which compares the most recent four quarters to the prior four quarters, increased by 6%, which represented a... » read more

FPGA Design Tradeoffs Getting Tougher
By Ann Mutschler - 16 Sep, 2019 - Comments: 0

FPGAs are getting larger, more complex, and significantly harder to verify and debug. In the past, FPGAs were considered a relatively quick and simple way to get to market before committing to the cost and time of developing an ASIC. But today, both FPGAs and eFPGAs are being used in the most demanding applications, including cloud computing, AI, machine learning, and deep learning. In some ... » read more

3D Power Delivery
By Brian Bailey - 12 Sep, 2019 - Comments: 1

Getting power into and around a chip is becoming a lot more difficult due to increasing power density, but 2.5D and 3D integration are pushing those problems to whole new levels. The problems may even be worse with new packaging approaches, such as chiplets, because they constrain how problems can be analyzed and solved. Add to that list issues around new fabrication technologies and an emph... » read more

Trading Off Power And Performance Earlier In Designs
By Ann Mutschler - 12 Sep, 2019 - Comments: 0

Optimizing performance, power and reliability in consumer electronics is an engineering feat that involves a series of tradeoffs based on gathering as much data about the use cases in which a design will operate. Approaches vary widely by market, by domain expertise, and by the established methodologies and perspective of the design teams. As a result, one team may opt for a leading-edge des... » read more

Place And Route Made Easier And Faster
By Mentor, a Siemens Business - 12 Sep, 2019 - Comments: 0

By Allan Crone A predictable trend in IC design is the ever-increasing size and complexity of designs while keeping the time allocated for the projects the same or shorter. Along with the tape-out pressure, organizations need to find cost savings everywhere possible. Lowering the overall cost of ownership of EDA tools is a viable way to manage the design budget. Consequently, design teams ar... » read more

Moving Beyond Assertions: An Innovative Approach to Low-Power Checking Using UPF Tcl Apps
By Mentor, a Siemens Business - 11 Sep, 2019 - Comments: 0

This paper uses examples and case studies to demonstrate how to leverage UPF 3.0 information model TCL query functions (aka Tcl Apps) and tool provided CLI commands to do low-power checking of a design. This is an innovative way to dynamically verify the low-power intent after simulation has completed and all waveforms are available. The paper also explains how users can write their own checker... » read more

Blog Review: Sept. 11
By Jesse Allen - 11 Sep, 2019 - Comments: 0

Cadence's Paul McLellan checks out the challenges of processing-in-memory and the steps involved in building a logic flow on a DRAM process. Synopsys' Taylor Armerding notes that with safety-critical software an ever-present factor in modern life, it's more necessary than ever to take the time to ensure quality and security when failures can be life-threatening. In a video, Mentor's Colin... » read more

Test On New Technology’s Frontiers
By SE Staff - 10 Sep, 2019 - Comments: 2

Semiconductor testing is getting more complicated, more time-consuming, and increasingly it requires new approaches that have not been fully proven because the technologies they are addressing are so new. Several significant shifts are underway that make achieving full test coverage much more difficult and confidence in the outcome less certain. Among them: Devices are more connected an... » read more

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