tag: Mentor

Crisis Ahead: Power Consumption In AI Data Centers
By Ed Sperling - 21 Jul, 2025 - Comments: 2

AI data centers are consuming energy at roughly four times the rate that more electricity is being added to grids, setting the stage for fundamental shifts in where power is generated, where AI data centers are built, and much more efficient system, chip, and software architectures. The numbers are particularly striking for the United States and China, which are in a race to ramp up AI data ... » read more

Chip Industry Week in Review
By The SE Staff - 18 Jul, 2025 - Comments: 0

The U.S. government will grant licenses to NVIDIA and AMD to again sell some AI chips — NVIDIA's H20 GPU and AMD's MI308 — to Chinese companies. TrendForce projects that the availability of NVIDIA chips, in particular, will create a surge in demand from Chinese AI firms and cloud service providers, and boost high-bandwidth memory (HBM) consumption. The move could raise China’s share of... » read more

A Better Path To Better 3D-IC Thermal Modeling
By Andras Vass-Varnai - 17 Jul, 2025 - Comments: 0

By Andras Vass-Varnai, Lee Wang, John Parry, Byron Blackmore, and Sudarshan Deo In an era where artificial intelligence, autonomous vehicles, and high-performance computing push the boundaries of semiconductor technology, the thermal management of 2.5D and 3D integrated circuits has become a make-or-break factor in product success. The traditional approach of treating thermal analysis as an ... » read more

Can Today’s Processor Architectures Be More Efficient?
By Bryon Moyer - 17 Jul, 2025 - Comments: 3

For years, processors focused on performance, and that performance had little accountability to anything else. Performance still matters, but now it must be accountable to power. If small gains in performance result in disproportionate power gains, designers may need to discard such improvements in favor of more power-efficient ones. Although current architectures undergo a steady cadence of... » read more

Finding And Fixing Leakage Between Power Domains
By Siemens EDA - 17 Jul, 2025 - Comments: 0

While there are many forms of current leakage in semiconductors, one especially nefarious type of leakage happens between power rails or power domains. Finding inter-domain leakage is vitally important for design reliability, especially in mixed power system design, but it is a known weakness of traditional electronic design automation (EDA) tools. Specialized EDA tools are needed to accurately... » read more

Blog Review: July 16
By Jesse Allen - 16 Jul, 2025 - Comments: 0

Synopsys' Bradley Geden and Manoz Palaparthi explain the difference between functional signoff and RTL signoff and why increased SoC complexity means that verification flows must now capture both the intent and the integrity of a design before it can move forward. Cadence's Frank Ferro finds that LPDDR isn't just for mobile devices anymore, with the new LPDDR6 standard bringing increased ban... » read more

AI In Chip Design: Tight Control Required
By Ed Sperling - 16 Jul, 2025 - Comments: 0

Executive Outlook: Semiconductor Engineering sat down with a panel of experts to talk about what's needed to effectively leverage AI, who benefits from it, and where software-defined hardware works best, with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Ze... » read more

Addressing Silicon Lifecycle Scaling Demands
By Marc Hutner - 10 Jul, 2025 - Comments: 0

In today’s competitive business landscape, navigating complexity can be a decisive advantage, but it also presents significant challenges. Three crucial trends driving the rise of complexity are technology scaling, design scaling and system scaling. Traditionally, Design for Test (DFT) solutions have focused on the die level; however, these challenges present opportunities at the package and ... » read more

Easing The Stress For Package-Level Burn-In
By Laura Peters - 10 Jul, 2025 - Comments: 0

Considered something of a necessary evil, burn-in of IC packages during production does a great job of weeding out latent defects so they don’t turn into failures in the field. But as AI and multi-chiplet packages become more common, and concerns about aging circuitry heighten, shifting stress testing to the wafer level looks increasingly attractive from a quality, throughput, and cost standp... » read more

How Advanced Packaging Is Reshaping Inspection
By Gregory Haley - 10 Jul, 2025 - Comments: 0

As semiconductor devices continue advancing into more sophisticated packaging schemes, traditional optical inspection technologies are brushing up against physical and computational boundaries. The growing reliance on 2.5D and 3D integration, hybrid bonding, and wafer-level processes has made it much harder to detect defects consistently and early enough to protect yields. While optical insp... » read more

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