tag: Mentor

Smarter DFT Infrastructure And Automation Emerge As Keys To Managing DFT Design Scaling
By Ron Press - 21 Dec, 2017 - Comments: 0

By Ron Press and Vidya Neerkundar The reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, and there are more DFT integration steps than ever before. The traditional approaches to DFT work on huge designs pose problems of repeatability and reliability... » read more

Is Verification Falling Behind?
By Brian Bailey - 21 Dec, 2017 - Comments: 1

Every year that [getkc id="74" comment="Moore's Law"] is in effect means that the [getkc id="10" kc_name="verification"] task gets larger and more complex. At one extreme, verification complexity increases at the square of design complexity, but that assumes that every state in the design is usable and unique. On the other hand, verification has not had the luxury that comes with design reuse b... » read more

Mixing Interface Protocols
By Ann Mutschler - 21 Dec, 2017 - Comments: 0

Continuous and pervasive connectivity requires devices to support multiple interface protocols, but that is creating problems at multiple levels because each protocol is based on a different set of assumptions. This is becoming significantly harder as systems become more heterogeneous and as more functions are crammed into those devices. There are more protocols that need to be supported to ... » read more

Creating Software Separation For Mixed Criticality Systems
By Mentor, a Siemens Business - 20 Dec, 2017 - Comments: 0

The continued evolution of powerful embedded processors is enabling more functionality to be consolidated into single heterogeneous multicore devices. Mixed criticality designs, those designs which contain both safety-critical and non-safety critical processes, can successfully leverage these devices and meet the regulatory requirements for IEC safety standards and the highest level of ISO. Thi... » read more

The Trouble With Models
By Ed Sperling - 20 Dec, 2017 - Comments: 0

Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Modeling is a way of abstracting the complexity in various parts of the semiconductor design, and there can be dozens of models required for complex SoCs. Some are ... » read more

Blog Review: Dec. 20
By Jesse Allen - 20 Dec, 2017 - Comments: 0

Mentor's Andrew Macleod points out five things that need to happen for autonomous and electric cars to move from R&D and test cases to mass-produced, commercially viable vehicles. Synopsys' Iain Singleton provides some tips on tackling large designs with formal and how the assume-guarantee technique helps split them without masking bugs. Cadence's Paul McLellan shares updates from the... » read more

The Week In Review: Design
By Jesse Allen - 15 Dec, 2017 - Comments: 0

M&A Synopsys finalized its acquisition of Black Duck Software, which provides software for managing and securing open source software in projects, adding to Synopsys' burgeoning software analysis and security business. The cash deal was approximately $547 million net of cash acquired. STMicroelectronics acquired Atollic, maker of the Eclipse-based TrueSTUDIO Integrated Development Envir... » read more

Co-Modeling Takes Emulation To The Next Level: System-Of-Systems
By Ron Squiers - 14 Dec, 2017 - Comments: 0

As designs move beyond System-on-Chip (SoC) to more complex System-of-Systems (SoS), it’s essential for design teams to effectively verify that these systems function together as intended. Increasingly, system design companies are turning to emulators as the only verification platform with the capacity and performance to validate that their SoC and SoS designs function as intended. Today�... » read more

Accounting For Power Earlier
By Ann Mutschler - 14 Dec, 2017 - Comments: 5

Concerns about power usage in an SoC are far from new, but the adoption of power management techniques still varies by company and by project. Leading semiconductor providers have made the necessary changes in tooling and methodology to account for [getkc id="106" kc_name="power awareness"] because they have to, but the rest of the industry hasn't necessarily caught up. “The companies t... » read more

EDA Challenges Machine Learning
By Brian Bailey - 14 Dec, 2017 - Comments: 1

Over the past few years, [getkc id="305" kc_name="machine learning"] (ML) has evolved from an interesting new approach that allows computers to beat champions at chess and Go, into one that is touted as a panacea for almost everything. While there is clearly a lot of hype surrounding this, it appears that machine learning can produce a better outcome for many tasks in the EDA flow than even the... » read more

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