tag: power

Wrestling With Analog At 3nm
By Brian Bailey - 09 Sep, 2021 - Comments: 0

Analog engineers are facing big challenges at 3nm, forcing them to come up with creative solutions to a widening set of issues at each new process node. Still, these problems must be addressed, because no digital chip will work without at least some analog circuitry. As fabrication technologies shrink, digital logic improves in some combination of power, performance, and area. The process te... » read more

Lowering Energy Per Bit
By Ann Mutschler - 12 Aug, 2021 - Comments: 0

Energy is emerging as a focal point in chip and system design, but solving energy-related issues needs to be dealt with on a much broader scale than design teams typically see. Energy is the amount of power consumed over a period of time to perform a given task, but reducing energy is a lot different than reducing power. It affects everything from operational costs and system performance to ... » read more

Do We Have An IC Model Crisis?
By Brian Bailey - 27 May, 2021 - Comments: 0

Models are critical for IC design. Without them, it's impossible to perform analysis, which in turn limits optimizations. Those optimizations are especially important as semiconductors become more heterogenous, more customized, and as they are integrated into larger systems, creating a need for higher-accuracy models that require massive compute power to develop. But those factors, and other... » read more

How Heterogeneous ICs Are Reshaping Design Teams
By Ed Sperling - 31 Mar, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the complex interactions developing between different engineering groups as designs become more heterogeneous, with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Mai... » read more

Optimizing Power Supply
By Cadence - 10 Feb, 2021 - Comments: 0

Any electrical engineer knows providing power to your board is a key feature in PCB design. While most boards can be functional, their true quality shines when the perfect level of power to components is achieved. Building and designing better power supplies is the best way to ensure the end-product has full life-cycle potential. But how do we ensure we can convert a (potentially variable) i... » read more

Von Neumann Upset
By Brian Bailey - 28 Jan, 2021 - Comments: 0

My recent article about the von Neumann architecture received some quite passionate responses, including one that thought I was attempting to slight the person. That was most certainly not the intent, given that the invention enabled a period of very rapid advancement in computers and technology in general. The process of invention and engineering are both quite similar and yet different. In... » read more

Testing More To Boost Profits
By Anne Meixner - 30 Dec, 2020 - Comments: 0

Not all chips measure up to spec, but as more data becomes available and the cost of these devices continues to rise, there is increasing momentum to salvage and re-purpose chips for other applications and markets. Performance-based binning is as old as color-banded resistors, but the practice is spreading — even for the most advanced nodes and packages. Over the last three decades, engine... » read more

Why It’s So Hard To Stop Cyber Attacks On ICs
By Ed Sperling - 23 Dec, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss security risks across multiple market segments with Helena Handschuh, security technologies fellow at Rambus; Mike Borza, principal security technologist for the Solutions Group at Synopsys; Steve Carlson, director of aerospace and defense solutions at Cadence; Alric Althoff, senior hardware security engineer at Tortuga Logic; and Joe Kiniry, princi... » read more

Chip-Package Co-Analysis Using Ansys RedHawk-CPA
By Ansys - 11 Nov, 2020 - Comments: 0

Ansys RedHawk-CPA is an integrated chip–package co-analysis solution that enables quick and accurate modeling of the package layout for inclusion in on-chip power integrity simulations using Ansys RedHawk. With RedHawk-CPA a designer can perform static IR drop analysis and AC hotspot analysis of the package layout following RedHawk static and dynamic analyses respectively. To ensure a reliab... » read more

Searching For Power Bugs
By Brian Bailey - 15 Oct, 2020 - Comments: 0

How much power is your design meant to consume while performing a particular function? For many designs, getting this right may separate success from failure, but knowing that right number is not as easy as it sounds. Significant gaps remain between what power analysis may predict and what silicon consumes. As fast as known gaps are closed, new challenges and demands are being placed on the ... » read more

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