tag: Siemens EDA

Unintended Patent Consequences
By Brian Bailey - 02 May, 2016 - Comments: 0

Section 101 of the U.S. patent law limits the types of things for which patent protection can be sought. It says: "Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title." In 2012, the Supreme Court made what they t... » read more

Cheap Money Effects
By Ed Sperling - 28 Apr, 2016 - Comments: 0

The mergers and acquisition activity that has reshaped the semiconductor industry over the past couple of years resembles a frenzy of acquisition activity that has occurred multiple times in previous boom years. But this round comes with a twist. It's being driven by historically low interest rates, which means it probably won't stop until interest rates rise and the cost of borrowing capital f... » read more

ESL Flow is Dead
By Brian Bailey - 28 Apr, 2016 - Comments: 3

It was 20 years ago that Gary Smith coined the term [getkc id="48" comment="Electronic System Level"] (ESL). He foresaw the next logical migration in abstraction up from the [getkc id="49" comment="Register Transfer Level"] (RTL) to something that would be capable of describing and building complex electronic systems. He also saw that the future of EDA depended upon who would control that marke... » read more

Way Too Much Data
By Ed Sperling - 28 Apr, 2016 - Comments: 0

Moving to the next process nodes will produce volumes more data, forcing chipmakers to adopt more expensive hardware to process and utilize that data, more end-to-end methodologies, as well as using tools and approaches that in the past were frequently considered optional. Moreover, where that data needs to be dealt with is changing as companies adopt a "shift left" approach to developing so... » read more

Bridging Hardware And Software
By Ann Mutschler - 28 Apr, 2016 - Comments: 1

The barriers between hardware and software design and verification are breaking down with more intricately integrated systems, bringing together different disciplines and tools. But there are lingering questions about exactly what this shift means design methodologies, team interactions, and what kind of training will be required in the future. Playing heavily into this is the fact that toda... » read more

System-Level Verification Tackles New Role
By Brian Bailey - 28 Apr, 2016 - Comments: 0

Wally Rhines, chairman and CEO of Mentor Graphics, gave the keynote at DVCon this year. He said that if you pull together a bunch of pre-verified IP blocks, it does not change the verification problem at the system level. That sounds like a problem. There are assumptions made that the IP blocks work to a reasonable degree, and that when performing system-level verification the focus is not a... » read more

Deep Space Design Considerations
By Nicolas Williams - 28 Apr, 2016 - Comments: 0

The linchpin technology in a deep space telescope is the ability to efficiently convert analog image sensor data into digital data in order to beam home high-resolution images of astronomical objects. The analog-to-digital converters (ADC) must perform flawlessly once deployed, because it is not feasible to drive out 1 million miles into space to fix any problems. The next-generation success... » read more

Analog-To-Digital Conversion Is Key For Deep Space Exploration With The James Webb Space Telescope
By Mentor, a Siemens Business - 27 Apr, 2016 - Comments: 0

Reflect back to your last design project. Did it have leading-edge requirements that seemed impossible at the time to fulfill? Now think about a design that needs to live in the harsh environment of space. A device that has to sip power and function flawlessly for over a decade because there is no opportunity to service it if anything goes wrong. That is the set of requirements that faced Dr. L... » read more

Blog Review: April 27
By Jesse Allen - 27 Apr, 2016 - Comments: 0

In a video, Cadence's Chris Rowan looks at the future of neural networks, particularly the shift from cloud-based to embedded devices and what we can increasingly expect from them. Waiting for RTL? Mentor's Rich Edelman suggests a way to get tests that are missing some simple RTL running with a bit of SystemVerilog. Synopsys' Richard Solomon provides a primer on calculating the bandwidth ... » read more

10nm Versus 7nm
By Mark LaPedus - 25 Apr, 2016 - Comments: 20

The silicon foundry business is heating up, as vendors continue to ramp their 16nm/14nm finFET processes. At the same time, they are racing each other to ship the next technologies on the roadmap—10nm and 7nm. But the landscape is complicated, with each vendor taking a different strategy. [getentity id="22865" e_name="Samsung"], for one, plans to ship its 10nm [getkc id="185" kc_name="fi... » read more

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