tag: Siemens EDA

Automated Chip Polishing Can Make Your Design Shine
By Bill Graupp - 21 May, 2015 - Comments: 1

Today’s modern chip design is a collaboration among many design teams, often using different design flows and different EDA tools. This state of the chip design industry can create high risk in the layout process, forcing delays in product release. To help reduce this risk, many levels of verification throughout the design flow exist to identify problematic areas in a design. While new EDA to... » read more

Blog Review: May 20
By Jesse Allen - 20 May, 2015 - Comments: 0

FinFETs change the equation for power optimization, says Mentor's Vincent Lebars – and while companies are attacking some power gains, there is much more to be had doing datapath optimization within the place and route flow. Cadence's Richard Goering talks with Oz Levia about the future direction of formal and its integration into other product lines now that the merger between Cadence and... » read more

Power Management Verification Requires Holistic Approach
By Ann Mutschler - 18 May, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss power management [getkc id="10" kc_name="Verification"] issues with Arvind Shanmugavel, senior director, applications engineering at [getentity id="22021" e_name="Ansys-Apache"]; Guillaume Boillet, technical marketing manager at [getentity id="22026" e_name="Atrenta"]; Adam Sherer, verification product management director at [getentity id="22032" e_... » read more

Week 49: Are We There Yet?
By Anne Cirkel - 15 May, 2015 - Comments: 0

When I was a little kid my parents would pack me and my sister into the car and drive to the Mediterranean for our summer camping vacation. It was quite a haul from our home on the west side of Germany near the border with Belgium to the south of France, and as is true of any long car trip, the last stretch was the hardest. After hours in the backseat, my sister and I would be craning our necks... » read more

Rethinking Power
By Ed Sperling - 14 May, 2015 - Comments: 0

Power typically has been the last factor to be considered in the PPA equation, and it usually was somebody else's problem. Increasingly it's everyone's problem, and EDA companies are beginning to look at power differently than in the past. While the driving forces vary by market and by process node, the need to save energy at every node and in almost all designs is pervasive. In the server m... » read more

Power Management Verification Requires Holistic Approach
By Ann Mutschler - 14 May, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss power management [getkc id="10" kc_name="Verification"] issues with Arvind Shanmugavel, senior director, applications engineering at [getentity id="22021" e_name="Ansys-Apache"]; Guillaume Boillet, technical marketing manager at [getentity id="22026" e_name="Atrenta"]; Adam Sherer, verification product management director at [getentity id="22032" e_... » read more

Correct-By-Design Methodology Requires Carefully Defined Constraints
By John McMillan - 14 May, 2015 - Comments: 0

Since the dawn of PCB usage, constraints have been an important part of the design. What are the dimensions? What weight of copper? Now, constraints have become much more than just physical dimensions. The most important constraints are defined by the design requirements of differential pairs, BGAs, low voltage devices, and high-speed parallel interfaces. The cost of rework skyrockets the fu... » read more

Why PCB Design Constraints Should Drive Your Design Flow
By Mentor, a Siemens Business - 13 May, 2015 - Comments: 0

This white paper will show you how a constraint-based PCB design can optimize the PCB design process, and improve time-to-market. See how with a correct-by-design methodology you can avoid integrity problems early in the design cycle, thus avoiding production delays and additional costs caused by required rework. Learn how PADS makes constraint management easy, intuitive, and time effective ... » read more

Blog Review: May 13
By Jesse Allen - 13 May, 2015 - Comments: 0

From corralling graphene electrons to the wild west of space, this week's top five from Ansys' Bill Vandermark reaches from the tiny to the immense. This summer, an asteroid mining firm plans to deploy a satellite to seek out mineral-rich space rocks. But someday, when mining asteroids is a commonplace affair, it may be archeologists who are doing the digging on distant planets. Could a smar... » read more

The Roadmap To 5nm
By SEMI - 11 May, 2015 - Comments: 0

By Debra Vogler Among the challenges the semiconductor industry will be facing as it moves down the path to node 5 are resistance-capacitance (RC) management and integration. SEMI is pleased to announce a SEMICON West 2015 STS technical program exploring these and other high-volume manufacturing challenges. According to An Steegen, SVP of Process Technology at imec, the list of RC managemen... » read more

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