tag: Siemens EDA

What’s Different At 16/14nm?
By Ed Sperling - 28 May, 2015 - Comments: 0

Will finFETs live up to their promise? It depends on whom you ask, when you ask that question, and the intended application of a design. But across the semiconductor industry, there is general agreement that it's getting easier to work at the most advanced nodes as tools and flows are better understood and overall experience increases. There is no question that [getkc id="185" kc_name="finFE... » read more

Full Coverage Or Full Monty
By Brian Bailey - 28 May, 2015 - Comments: 1

Without adequate coverage metrics and tools, verification engineers would never be able to answer the proverbial question: Are we done yet? But a lot has changed in the design flow since the existing set of metrics was defined. Does it still ensure that the right things get verified, that time is not wasted on things deemed unimportant or a duplication of effort, and can it handle today’s hie... » read more

Rethinking Patents
By Brian Bailey - 28 May, 2015 - Comments: 0

Over the past few years the pressure on the patent system as a means of protecting intellectual property has been tested to the limit, and many changes are being made in an attempt to keep it viable. But in an age of globalization, coupled with the fact that for the patent system to work there has to be an infrastructure of suitable enforcement, it may be time to rethink its viability—especia... » read more

Addressing Design Challenges In Heterogeneous Multicore Embedded Systems
By Mentor, a Siemens Business - 27 May, 2015 - Comments: 0

Single-core processor designs for purpose-built devices used to rule the day. Now, heterogeneous multicore systems are quickly becoming the de facto architecture as devices are tasked to do more complex functions faster and more efficiently. In this paper, we’ll explore why hetero/multicore systems have become so popular and why many of our current procedures and practices must change if we a... » read more

Blog Review: May 27
By Jesse Allen - 27 May, 2015 - Comments: 0

With the launch of UNICEF and ARM's 'Wearables for Good' design challenge, David Maidment digs into the program's details and how unobtrusive wearables and sensor technology benefits not only consumers in affluent countries, but could improve conditions for those in the developing world as well. From an ultracompact beamsplitter that could boost processing power for supercomputers within the... » read more

Tortuga Logic: Hardware Security
By Ed Sperling - 26 May, 2015 - Comments: 0

For the Internet of Things to really get rolling, it has to be bulletproof. And given the number of very high-profile security breaches in recent months, it has a long way to go before consumers or businesses will feel comfortable using any of a new wave of smart devices That concern has prompted a wave of acquisitions from companies such as Intel (McAffee), Cadence (Jasper Design Automation... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 22 May, 2015 - Comments: 0

At an event, Samsung rolled out its 10nm finFET technology. The company also showed a 300mm wafer with 10nm finFET transistors. "We have silicon-based PDKs out," said Kelvin Low, senior director of foundry marketing for Samsung. Samsung plans to move into production with its 10nm finFET technology by the end of 2016, he said. IC Insights released its chip rankings in terms of sales in the fi... » read more

The Week In Review: Design/IoT
By Jesse Allen - 22 May, 2015 - Comments: 0

Tools Cadence updated its Allegro PCB product line with a new manufacturing option that accelerates manufacturing documentation and technology updates for increased efficiency, control and productivity for designers and streamlining handoff to manufacturing. The release also allows users to develop custom fabrication and assembly rules. Invionics expanded its Invio EDA development platfor... » read more

How Hard Is FD-SOI Design?
By Ann Mutschler - 21 May, 2015 - Comments: 0

Fully-depleted silicon-on-insulator ([getkc id="220" kc_name="FD-SOI"]) manufacturing technology reached of point of readiness for mass production at the end of March. Along with that, it’s now clear that while there are some impacts on the design flow, those impacts are not game changers. For one thing, the tools required are the same ones currently used for 28nm planar bulk CMOS. The onl... » read more

Next-Generation Parasitic Extraction For 16nm And Beyond
By Mentor, a Siemens Business - 21 May, 2015 - Comments: 0

Advanced nodes and innovative process features such as finFET transistors require a leap forward in the performance and accuracy of analysis tools. The new Calibre xACT solution is a high-performance, high-accuracy parasitic extraction tool architected from the top-down for diverse IC design styles at advanced nodes. The Calibre xACT product delivers reference-level accuracy for leading-edge fi... » read more

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