tag: Siemens EDA

Incremental Design Methodologies
By Brian Bailey - 26 Feb, 2015 - Comments: 0

There are times when we become stuck in the past, or choose to believe something that is no longer true or actually never was true. As we get older, we are all guilty of that. History tends to rewrite itself, especially given that this industry is aging. One of these situations occurred recently, and comments from an industry luminary didn’t align with the thoughts and memories of other peopl... » read more

Custom Versus Platform Design
By Ed Sperling - 26 Feb, 2015 - Comments: 0

The increase in [getkc id="81" kc_name="SoC"] complexity is being mirrored by a rise in complexity within the markets that drive demand for those chips. The upshot is that a push toward greater connectivity, lower power and better performance—and all for a minimal cost—has turned the pros and cons for custom design vs. platforms and superchips into a murky decision-making process. For t... » read more

First Time Success And Cost Control
By Brian Bailey - 26 Feb, 2015 - Comments: 0

First time success has been the ultimate goal for semiconductor companies due to escalating mask costs, as well as a guiding objective for the development of EDA tools, especially in the systems and verification space. These pressures are magnified for the [getkc id="76" comment="Internet of Things"] (IoT), especially the edge devices. Have system-level tools been able to contribute to first ti... » read more

Defining Functional Accuracy
By Jon McDonald - 26 Feb, 2015 - Comments: 0

I have been heavily involved in a project that recently completed. It involved creating virtual platforms (VPs) for a number of Altera’s FPGA SoCs. If you’re interested in more information, an announcement on the VP availability went out last week. Some of the modeled platforms existed and some were in various stages of development. The goal of the project was to deliver functionally acc... » read more

Debug This!
By Mentor, a Siemens Business - 25 Feb, 2015 - Comments: 0

Class-based debug is not the same as debugging RTL. You don’t have to be an object-oriented programmer in order to debug a class-based testbench, which is just a bunch of objects – some statically created, some dynamic – which interact with the DUT. The upshot? Class based debug doesn’t have to be hard! To read more, click here. » read more

Blog Review: Feb. 25
By Jesse Allen - 25 Feb, 2015 - Comments: 0

Synopsys' Aron Pratt continues his series on SystemVerilog interfaces and strategies for dealing with parameterization. There are workarounds to the problems it introduces, but they come with a price. Mentor's John Day digs into Volvo's plans for autonomous autos. There are a lot of speedbumps ahead, and while it's easy to build a self-driving concept vehicle, actually getting on the road is... » read more

Week 37: Eliminating Glitches In The Matrix
By Anne Cirkel - 20 Feb, 2015 - Comments: 0

As I’ve often stated, DAC is very much a team effort. Way back in week five I introduced Chuck Alpert, who is vice chair of the conference. Among other things, this title means Chuck will chair DAC 53 in Austin in 2016. Not that he hasn’t been busy with DAC 52. Chuck worked very hard to put together this year’s conference matrix, basically the overall conference schedule. It was big job, ... » read more

The Week In Review: Design/IoT
By Jesse Allen - 20 Feb, 2015 - Comments: 0

Deals Arteris teamed up with Yogitech to integrate the two companies' products. They're planning a set of ISO 26262 deliverables for a series of SoC reference designs and a functional safety assessment of the Arteris FlexNoC interconnect IP. ARM and Green Hills Software collaborated on an optimized compiler for the Cortex-R5 processor. The compiler achieved a score of 1.01EEMBC Automarks/... » read more

How To Extend Litho Scaling
By Ann Mutschler - 19 Feb, 2015 - Comments: 0

IC mask [getkc id="80" comment="lithography"] today is sophisticated and complex. It's also a work in progress with a lot of unknowns as the industry struggles to increase productivity while reducing risk. The bulk of the work currently is focused on trying to figure out what would be a practical scheme for patterning lithography that could be used at 10nm and 7nm, said Gandharv Bhatara, Ca... » read more

Demonstrating The Benefits Of Source-Mask Optimization And Enabling Technologies Through Experiment And Simulations
By Mentor, a Siemens Business - 19 Feb, 2015 - Comments: 0

In recent years the potential of Source-Mask Optimization (SMO) as an enabling technology for 22nm-and-beyond lithography has been explored and documented in the literature. It has been shown that intensive optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the mask and the source, which leads to improved lithograp... » read more

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