tag: Siemens EDA

Motorcycle Diaries
By Jon McDonald - 26 Jul, 2012 - Comments: 0

By Jon McDonald I recently had reason to add another vehicle to my household. My son is starting to drive, so he's taking my car. Instead of another car I decided to get a motorcycle. I have had a couple, but it's been a few years. After much browsing I decided on a Ducati, I picked it up a few weeks ago. It has an impressive number of user adjustable electronic controls, everything from AB... » read more

Achieving Fast And Accurate Extraction Of 3D-IC Layout Structures
By Various Writers - 26 Jul, 2012 - Comments: 0

The electronics industry is devoting a lot of energy to exploring “More than Moore’s Law” approaches that drive continued value scaling through system integration, rather than (or in addition to) shrinking transistors. One of the most promising techniques is the creation of 3D-ICs using TSV structures. However, accurately modeling a 3D multi-die system requires tools that extract precise ... » read more

More Design Rules Ahead
By Ed Sperling - 25 Jul, 2012 - Comments: 0

By Ed Sperling & Mark LaPedus For those companies that continue to push the limits of feature shrinkage, designs are about to become more difficult, far more expensive—and much more regulated. Two converging factors will force these changes. First, the limits of current 193nm immersion lithography mean companies now must double pattern at 20nm, and potentially quadruple pattern at 14n... » read more

Experts At The Table: Multipatterning
By Ed Sperling - 20 Jul, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung Ele... » read more

Four Factors Driving Processor Choices
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ed Sperling Choosing processors for an SoC, a system-in-package, or even a complete system is becoming much more difficult, and the challenge is growing as demands on performance, power, area and time to market continue to increase. There are many reasons why this is becoming more difficult—and some designs will require more tradeoffs than others, depending upon IP re-use or a particul... » read more

Dealing With Variability
By Barry Pangrle - 12 Jul, 2012 - Comments: 0

By Barry Pangrle Process, voltage and temperature, a.k.a. PVT, are well known to designers who are working to complete “signoff” for their designs. In order for a design to be production-ready, it’s necessary to ensure that the design is going to yield parts at a sufficiently high percentage for profitability and that it will still operate within the expected variation of the process and... » read more

Bubble Gum and Scotch Tape
By Ann Mutschler - 12 Jul, 2012 - Comments: 0

It’s always extremely interesting to talk with actual design engineers, trudging through the trenches of challenges like 3D design. Recently, I was able to speak with Robert Patti, chief technology officer, vice president of design engineering and a director at Tezzaron Semiconductor. The company has been putting 3D designs together for quite some time so I expected to hear that they are u... » read more

Monsters, Inc.: How Do I Fix These Double Patterning Errors Anyway?
By David Abercrombie - 29 Jun, 2012 - Comments: 0

By David Abercrombie Just mention double patterning (DP) to designers, and you can see the fear in their eyes. There is real trepidation about what kind of monster DP design debugging will be. In this article, I hope to alleviate some of that trepidation by educating you on manual correction techniques, automated fixing hints, and automated fixing capabilities you can adopt to help you with DP... » read more

Experts At The Table: Improving The Efficiency Of Software
By Ed Sperling - 29 Jun, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Design sat down to talk about how to write better software with Jan Rabaey, Donald O. Pederson Distinguished Professor at the University of California at Berkeley; Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Emily Shriver, research scientist at Intel; Alan Gibbons, principal engineer at Synopsys; and Dav... » read more

Emulation’s Winding Path To Success
By Ed Sperling - 28 Jun, 2012 - Comments: 0

By Ed Sperling Emulation was developed for verifying complex ICs when simulation was considered too slow. After more than a decade of very slow growth, however, sales have begun to ramp. There are several reasons for this shift. First, SoCs simply are becoming more complex, and the amount of verification that needs to be done to get a chip out the door can bring simulation to a crawl. Desig... » read more

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