tag: Siemens EDA

Experts At The Table: Multi-Foundry Strategies
By Ed Sperling - 26 Jul, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing and Design sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; John Murphy, director of strategic alliances marketing at Cadence; Michael Buehler-Garcia, director of Calibre design solutions marketing at Mentor Graphics; Bob Smith, vice president of marketing and business development at Magma, and Linh Hong, vice president ... » read more

Design For Power Methodology
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ann Steffora Mutschler It is rare to find an advanced chip today that has not been designed considering power from the very earliest point. In fact, it is safe to say that power is the No. 1 priority, or a close No. 2. But to achieve the highest performance for a low-power design, a design-for-power methodology is necessary, comprised of the capabilities to implement power in the most ef... » read more

Building A Better CMOS FET
By Barry Pangrle - 21 Jul, 2011 - Comments: 0

By Barry Pangrle SEMICON West was held last week in San Francisco and I had the opportunity to attend the Emerging Architectures session. Serge Biesemans, vice president of process technology at Imec, gave a nice overview presentation on FinFETs. From a power and performance standpoint, we’ve seen some early pre-production information released from Intel that I briefly discussed here. Serge�... » read more

Blog Review: July 20
By Ed Sperling - 20 Jul, 2011 - Comments: 0

By Ed Sperling Synopsys’ Eric Huang pays a visit to the Microsoft Store and finds a really smart salesperson who seems to know just about everything there is to know about the products for sale. And yes, that is somewhat unexpected. Cadence’s Jean-Michel Fernandez talks about creating SystemC peripheral models. Fernandez represents Cadence’s Team ESL, which is an interesting developme... » read more

Going With The Flow
By Ed Sperling - 15 Jul, 2011 - Comments: 0

It’s hard to judge things in isolation, but a continuum of acquisitions in the low-power area is proving just how important power considerations have become to hardware and software design, verification and manufacturing flows. Over the past couple of years acquisitions by Synopsys in the virtual prototyping arena, and Mentor Graphics in the test and embedded software area, have included p... » read more

The Challenge of 3D
By Ed Sperling - 06 Jul, 2011 - Comments: 0

Juan Rey, senior director of engineering for Mentor Graphics' Design To Silicon Division, talks about 3D stacking and 3D structures on chips. [youtube vid=YiH5IkxiEHU] » read more

2.5D Stacking And Test
By Ed Sperling - 06 Jul, 2011 - Comments: 0

Michael Buehler-Garcia, director of Calibre Design Solutions marketing at Mentor Graphics, talks about the challenges in building 2.5D stacks and how testing them will become a major headache. [youtube vid=tLKdOo5L8C8] » read more

A Smart Filling Solution Yields Multiple Benefits
By Mentor Graphics Staff Writers - 01 Jul, 2011 - Comments: 0

By Jeff Wilson, A return on investment doesn’t happen until customers actually buy your product, so the most fundamental goal for designers is getting their designs to market. While there are numerous steps along the way, one task that must be performed is adding fill to the design. Fill is like design rule checking (DRC)—it’s not an optional step, because it is needed to ensure the manu... » read more

Different Ways To Boost Yield
By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Ann Steffora Mutschler In the race to get products to market with shortening product cycles, steepening the ramp to yield is critical. The introductory phase of a product is the point at which margins are highest and market share can be most easily gained. This is no surprise to chipmakers. What is surprising is just how much more difficult it has become to achieve acceptable yield quick... » read more

Virtual Prototyping Takes Off
By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Ann Steffora Mutschler Skyrocketing software development costs, which for years have been “somebody else’s problem,” are now firmly part of the SoC development teams list of headaches. That has made virtual prototyping far more popular, particularly at 40nm and beyond, where engineers are looking at this approach as a way of managing complexity, doing architectural exploration and eve... » read more

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