tag: Siemens EDA

Heat Wreaks Havoc
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler As semiconductor manufacturing technology has scaled ever smaller, the density of power grid networks has caused on-chip temperatures to rise, negatively impacting performance, power, and reliability. CMOS technology, still the predominant material in SoCs, was originally conceived as a low-power technology when compared with the bipolar approach, which was a very... » read more

Interconnect Power II
By Barry Pangrle - 08 Sep, 2011 - Comments: 0

Barry Pangrle After submitting last month’s blog, I read a very interesting article by Deepak Sekar analyzing Intel’s 22 nm FinFET technology versus a hypothetical planar 22nm CMOS technology. Beyond the advantages of being able to use a 140 mV reduction in the supply voltage for the trigate technology, Deepak did a breakdown analysis for the predicted power across a representative micropr... » read more

Support the Arts! in Custom Design Verification
By Mentor Graphics Staff Writers - 01 Sep, 2011 - Comments: 0

By Joe Davis Increasing numbers of integrated circuits (ICs) are targeted at mobile/wireless applications. The amount of analog content in these ICs is also increasing, reflecting strong growth in wireless technologies such as WiFi, Bluetooth, 3G, and 4G, as well as GPS, audio, imaging, and sensor technologies. Market research indicates that while analog circuitry occupies only 20% of the ar... » read more

Testing One, Two, Three
By Ed Sperling - 25 Aug, 2011 - Comments: 0

By Ed Sperling The rule of thumb at 90nm—still one of the mainstream process nodes—has been that test is something you do when a chip is done. You attach electrodes on either side, make sure the signal comes through clearly, and that the SoC functions properly. Try the same thing at 40nm, with multiple power islands, multiple voltage rails, lots of third-party IP and usually a slew of p... » read more

Which Came First?
By Jon McDonald - 25 Aug, 2011 - Comments: 0

By Jon McDonald Which came first the chicken or the egg? Based on some of my recent discussions I could ask the question in a slightly different way: “Which came first, the hardware or the software?” Depending on your point of view and personal bias the answer may appear obvious, but from what I've seen it can be very dependent on your current engineering situation. Adopting one perspectiv... » read more

Experts At The Table: Multi-Foundry Strategies
By Ed Sperling - 22 Aug, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing and Design sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; John Murphy, director of strategic alliances marketing at Cadence; Michael Buehler-Garcia, director of Calibre design solutions marketing at Mentor Graphics; Bob Smith, vice president of marketing and business development at Magma, and Linh Hong, vice president ... » read more

Interconnect Power
By Barry Pangrle - 11 Aug, 2011 - Comments: 0

By Barry Pangrle Applied Materials announced its latest version of nano-porous low-k dielectric technology called Black Diamond 3 last month at Semicon West. What really caught my ear though was the marketing claim that 1/3 of total chip power consumption (really energy) is in the interconnect. I thought about this a bit, and certainly for some designs this seemed to easily be quite po... » read more

3D Stacking: A Reality Check
By Ed Sperling - 28 Jul, 2011 - Comments: 0

By Ed Sperling The first 2.5D and 3D chips are expected to arrive next year, with the mainstream chip market expected to follow in 2013. While this trend already has seen its share of hype, stacked die—whether through a series of TSVs in true 3D or through an interposer layer in 2.5D—is as real as Moore’s Law. In fact, it’s a direct result of Moore’s Law. But unlike the progres... » read more

Start The Revolution
By Jon McDonald - 28 Jul, 2011 - Comments: 0

By Jon McDonald “Know thyself.” That advice is promoted in so many different forms it's hard to know where it started. I have been involved in a number of projects recently in which these words would have greatly simplified the project flow. “Simplified” is probably not quite the right word. The issue in this case is not to simplify the project, but to properly understand, characterize... » read more

Debugging Double Patterning without Getting Double Vision
By David Abercrombie - 27 Jul, 2011 - Comments: 1

By David Abercrombie Given that my last couple of blogs on double patterning (DP) might have scared you to death, I figured it was time to bring you some good news. It is unavoidably true that double patterning layout constraints at 20nm and below are going to require changes in all aspects of the design flow, but Mentor Graphics (and, I am sure, the rest of the EDA industry) is working very... » read more

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