tag: Siemens EDA

Thermal Modeling Held Back By Outdated Standards
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler As the reality of true 3D IC design nears, engineering teams are keen to manage the heat between the stacked die in order to avoid catastrophic failures. Thermal modeling tops the roster of techniques to leverage in this area. Herve Jaouen, director of modeling and simulation in STMicroelectronics’ technology R&D organization, explained that in 3D designs the... » read more

Energy Vs. Power
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler The terms power and energy are used almost interchangeably these days, but understanding and clearly articulating how to optimize embedded designs for maximum energy and power efficiency can make a big difference in a design. At a physics level, energy = power x time, whereas power is the rate of energy in a given time window. When the focus is specifically power, ... » read more

The Hidden Costs Of Test
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ed Sperling As complexity grows in SoCs, so does the ability to accurately test them. That helps explain why there are so many different types of tests and so much confusion about what to use to perform those tests, when to test, and where in the flows to include those tests. But what’s less well known is that tests done improperly also can give false results, labeling good chips as bad�... » read more

Intel’s Claremont Near-Threshold Voltage IA Core
By Barry Pangrle - 06 Oct, 2011 - Comments: 0

By Barry Pangrle Intel announced many new technologies at its recent Intel Developer Forum (IDF) held from Sept. 13-15 in San Francisco, but the one announcement that jumped out at me was the unveiling of its work on a near-threshold voltage (NTV) processor named “Claremont.” For this exercise, Intel chose an older Pentium design to help minimize the number of variables the engineers would... » read more

Are We There Yet?
By Ann Mutschler - 06 Oct, 2011 - Comments: 0

We’ve been talking in the industry for as long as I can remember about hardware and software co-design and I’m always curious to hear how that it progressing….or not. I posed this question to Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation synthesis group who is constantly in touch with engineering teams. His take is that hardware and software teams are... » read more

Solid Verification Methodology Essential To Productivity
By Ann Mutschler - 22 Sep, 2011 - Comments: 0

Verifying SoCs from a functional perspective pushes the limits of already lean resources, driving verification teams to seek out new ways to improve productivity of verification tasks. Of course, with the verification task being a time-bound one, the challenge is daunting. It is well understood that consumer electronics is pushing the technology envelope in terms of the amount of technology ... » read more

20nm IP Portability Appears Virtually Impossible
By Ed Sperling - 22 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler Each node on the deep submicron path has brought new challenges to engineering teams, and 20nm is no different. With EUV (extreme ultraviolet) lithography challenges still being worked out, double patterning (DP) instead will be embraced in the manufacturing process most likely until 10nm. Due to the unique nature of DP, IP portability between foundries will become a ... » read more

More Intelligent Verification
By Jon McDonald - 22 Sep, 2011 - Comments: 0

By Jon McDonald If I have flipped a coin 1,000 times and it's come up heads every time what are the odds that I will get another head on the next flip? The odds on the next flip are still 50/50. The fact that I observe a uniquely unlikely situation has no impact on my current probability, and frankly any sequence of prior results would be equally unlikely. I find some of the same thinking appl... » read more

DFT: Essential For Power-Aware Test
By Ed Sperling - 18 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler Power-aware test is a major manufacturing consideration due to the problems of increased power dissipation in various test modes, as well as test implications that come up with the usage of various low-power design technologies. Challenges for test engineers and test tool developers include understanding the various concerns associated with power-aware test, develo... » read more

Multi-Patterning: Game Changer or Y2K?
By Mentor Graphics Staff Writers - 14 Sep, 2011 - Comments: 0

By Joe Davis, Mentor Graphics Every new technology node brings new process challenges that translate into design challenges. For the last five years, design rules and processes have had to deal with an increasing impact from nearest-neighbor and environmental effects from lithography, stress, and temperature. Where once cells could be designed and placed independently, now a cell’s real pe... » read more

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