tag: Siemens EDA

Verifying Low-Power IP And Designs
By Ed Sperling - 13 Mar, 2009 - Comments: 0

By Ed Sperling Verification has always been the time-consuming part of designs. Even at 120nm and above, where power wasn’t much of an issue, verification accounted for an estimated 70 percent of the non-recurring engineering expense in a chip. Since then, the tools to automate design have become more effective, but the complexity of designs has grown by leaps and bounds beyond those tools.... » read more

ESL Languages: Which One Is Right For Your Needs?
By Jon McDonald - 19 Feb, 2009 - Comments: 0

The question about ESL language is the right one comes up over and over again.  As customers begin to understand the benefits of modeling and analysis at the system level, they must address this question as one of the first steps in getting started.   What language should be used for ESL—SystemC, SystemVerilog, UML or M? Technically, you can create an ESL/TLM platform in any language yo... » read more

The In’s And Out’s Of Parasitic Extraction
By Ed Sperling - 07 Feb, 2009 - Comments: 0

Low-Power Engineering sat down with two of the top experts—Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys, and Carey Robertson, Calibre product marketing director at Mentor Graphics—to talk about what changes at 28nm and 22nm and why parasitic extraction is becoming so important. [youtube vid=JXnUWN1uwGQ] » read more

ESL Modeling: Be Careful What You Wish For
By Jon McDonald - 27 Jan, 2009 - Comments: 0

I was talking to a customer last week about his most recent ESL activities and he brought up a question that I’ve heard from many different sources : “How accurate does my ESL model need to be?” The level of timing accuracy, and even function accuracy, needed for effective system level analysis is a very dynamic question, with different answers for different organizations, and even di... » read more

IP Consolidation Improves Reliability
By Ann Mutschler - 22 Jan, 2009 - Comments: 0

By Ann Steffora Mutschler As individual blocks of IP in an IC design grow to more than 1 million gates, making sure each block functions reliably and interfaces with the system properly is a make-or-break scenario for many companies. For one thing, getting it right is absolutely critical as the semiconductor industry reaches its maturity point with margins harder to reach. Coupled with an ind... » read more

New Pain Points In System-Level Design
By Ed Sperling - 22 Jan, 2009 - Comments: 0

By Ed Sperling One of the strange things about downturns is they force companies to re-examine what they do and question what kind of value they bring to the market. This is particularly true in the semiconductor world, where the average selling prices for chips has been sliding for the better part of two decades. In the case of the chip industry, which is heavily cyclical, that leaves lo... » read more

Who’s Out, Who’s In
By Ed Sperling - 21 Jan, 2009 - Comments: 0

The EDA world is either doing better than most segments of the economy or coming apart at the seams, depending upon your perspective and your definition of exactly what an EDA company is. But at least one trend seems clear: As we push into the world of system-level design from chip design and SoCs instead of ASICs, the high-level trend is broader companies with more complete integrated packag... » read more

Not Everyone Feels The Pinch
By Ed Sperling - 18 Jan, 2009 - Comments: 0

By Ed Sperling In the midst of the longest and deepest downturn since the invention of the transistor, not everyone is doing badly. In fact, there are some bright spots across the electronics industry that seem to defy gravity, so to speak. In particular, design tools are doing well. When the industry is down, they’re typically down less because, as any successful executive in technolog... » read more

The ESL Conundrum
By Ann Mutschler - 17 Dec, 2008 - Comments: 0

As Moore’s Law continues its relentless march, the “electronic system level” (ESL), which is the next higher level of abstraction above the register transfer level (RTL), continues to be adopted as an answer to the ever-increasing complexity of designing semiconductors. Although ESL emerged about five years ago, the term itself still can confound the very community that seeks to embrac... » read more

Moving Up The Food Chain
By Ed Sperling - 17 Dec, 2008 - Comments: 0

By Ed Sperling It used to be considered axiomatic that chip companies would be rewarded for spectacular technology, reflected in the market value of their components and in their stock price. But with stock prices routinely getting hammered even before the downturn, many companies have begun to re-think their mission. National Semiconductor, for one, is looking at creating modules rather than... » read more

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