tag: Siemens

Portable Stimulus Status Report
By Brian Bailey - 24 Aug, 2017 - Comments: 0

The first release of the Portable Stimulus (PS) standard is slated for early next year. If it lives up to its promise, it could be the first new language and abstraction for verification in two decades. [getentity id="22028" e_name="Accellera"] uncorked the PS Early Adopter release at the Design Automation Conference (DAC) in June. The standard has been more than two years in the making by t... » read more

When Is Verification Complete?
By Ann Mutschler - 24 Aug, 2017 - Comments: 0

Deciding when verification is done is becoming a much more difficult decision, prompting verification teams to increasingly rely on metrics rather than just the tests listed in the verification plan. This trend has been underway for the past couple of process nodes, but it takes time to spot trends and determine whether they are real or just aberrations. The Wilson Research Group conducts a ... » read more

Frontloading CFD-Required Technologies
By Mentor, a Siemens Business - 23 Aug, 2017 - Comments: 0

Today, manufacturing product design cycles need to get shorter and shorter as either new or increased numbers of products get to the market faster. In the automotive industry for example, with either facelifts to existing car models, or the next generation of the model appearing almost every 3-4 years, and an increasing number of new models appearing on the market, the demand on engineering des... » read more

Blog Review: Aug. 23
By Jesse Allen - 23 Aug, 2017 - Comments: 0

Cadence's Madhavi Rao asks whether India should have more fabs and the role government policy should play. Synopsys' Kapil Rajpal checks out the Serial Peripheral Interface, which is emerging as a popular choice in automotive applications, and various vendor specific flavors. In a video, Mentor's Colin Walls explains inter-task communication and the basic mechanisms of how to pass data fr... » read more

Blog Review: Aug. 16
By Jesse Allen - 16 Aug, 2017 - Comments: 0

Cadence's Paul McLellan checks out how Imec sees the future of transistors and the challenges of 3D logic. Synopsys' Robert Vamosi gets a lesson on the electronic systems powering modern cars, and considers when it's ethical to hack one. Mentor's Colin Walls takes a look at how to pass data between RTOS tasks. Rambus' Aharon Etengoff looks at recent semi market predictions, from expand... » read more

How Reliable Are FinFETs?
By Ann Mutschler - 16 Aug, 2017 - Comments: 1

Stringent safety requirements in the automotive and industrial sectors are forcing chipmakers to re-examine a number of factors that can impact reliability over the lifespan of a device. Many of these concerns are not new. Electrical overstress (EOS), electrostatic discharge (ESD) and [getkc id="160" kc_name="electromigration"] (EM) are well understood, and have been addressed by EDA tools f... » read more

The Week In Review: Design
By Jesse Allen - 11 Aug, 2017 - Comments: 0

M&A Mentor acquired Valydate, provider of the VERA schematic integrity analysis tool. Founded in 2010, the Canadian company also offered signal and power integrity and static timing analysis services. Valydate's technology will be integrated with Mentor's Xpedition PCB design flow, though former Valydate CEO Michael Alam says it will continue to serve all EDA environments. Tools Aldec ... » read more

UPF Power Domains And Boundaries
By Progyna Khondkar - 10 Aug, 2017 - Comments: 0

The Universal Power Format (UPF) plays a central role in mitigating dynamic and static power in the battle for low-power in advanced process technology. A higher process node is definitely attractive as more functionality integration is possible in a smaller die area at a lower cost. However, in reality, this comes at the cost of exponentially increasing leakage power. This is because the minim... » read more

Addressing The Complex Challenges In Low-Power Design And Verification
By Mentor, a Siemens Business - 09 Aug, 2017 - Comments: 0

This paper provides a comprehensive analysis of various complex debug problems faced in low-power design and verification. By using relevant examples it demonstrates how these issues can be either avoided or easily solved. We will also highlight some of the common pitfalls that low-power designers can avoid, which otherwise can lead to complex low-power issues that are difficult to debug at lat... » read more

Blog Review: Aug. 9
By Jesse Allen - 09 Aug, 2017 - Comments: 0

Cadence's Paul McLellan digs into a recently discovered vulnerability in the Broadcom Wi-Fi chip used in many smartphones and why it should be a wakeup call for SoC designers. Mentor's Craig Armenti considers whether work-in-process design data management is an asset or a liability. Synopsys' Thomas M. Tuerke notes that in code, as in medicine, proper hygiene is should be treated as a con... » read more

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