Programmable Hardware Delivers 10,000X Improvement In Verification Speed Over Software For Forward Error Correction


In the race to increase the speeds of wireline networking and communications, forward error correction (FEC) has become a vital part of the toolkit. To function effectively, especially with the increasing use of four-level pulse amplitude modulation (PAM4), high-speed protocols need FEC to avoid a rise in the number of reception errors. Each incremental increase in the transmitted symbol rate r... » read more

Digital Engineering Transforms Chips For The Future


The semiconductor industry stands at a critical turning point. With global semiconductor sales exceeding $600 billion last year, the need for the industry to scale has never been more apparent. As AI applications drive unprecedented requirements for processing capabilities, chip designers are turning to advanced simulation technologies to enable the digital engineering workflows that will sup... » read more

Best Practices to Optimize Infrastructure for Simulations


Our Best Practices Guide equips you with expert strategies for leveraging high-performance computing (HPC) to maximize Ansys workload efficiency and overcome common challenges. As simulation complexity increases, a robust computing infrastructure is essential for rapid and large-scale modeling. Modern HPC systems provide: High-core-count CPUs for superior memory and compute perfo... » read more

GPU Acceleration Of Rigorous Lithography Simulations


Producing modern semiconductor devices is an immensely challenging process. Successful execution entails advanced process nodes, novel device architectures, new materials, and many fabrication steps. One especially challenging area is lithography, in which light is sent through a photomask, passes through a projection system of lenses and mirrors, and strikes the substrate to create the device ... » read more

EBook: Optimizing Analog Design With Multiphysics


As technologies like artificial intelligence (AI), 5G, electric vehicles, and high-speed computing continue to advance, analog and mixed-signal (AMS) technologies have become the unsung heroes of next-gen electronics. AMS chips are enabling smarter, faster, and more efficient systems, but traditional design approaches are struggling to keep pace. Interconnect parasitics, power integrity, photo... » read more

AI In Chip Design: Tight Control Required


Executive Outlook: Semiconductor Engineering sat down with a panel of experts to talk about what's needed to effectively leverage AI, who benefits from it, and where software-defined hardware works best, with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Ze... » read more

HW Security: A Hybrid Verification Method Combining Simulation And Formal Verification (RPTU, UCSD)


A new technical paper titled "FastPath: A Hybrid Approach for Efficient Hardware Security Verification" was published by researchers at RPTU Kaiserslautern-Landau and UC San Diego. "We propose FastPath, a hybrid verification methodology that combines the efficiency of simulation with the exhaustive nature of formal verification. FastPath employs a structural analysis framework to automate th... » read more

Simplify Simulation With Reduced-Order Modeling


One of the biggest challenges in engineering and design is striking a balance between accuracy and speed. Development teams strive for precision but must often accelerate their simulation and computational workflows to meet production demands. Although physics-based, high-fidelity simulations are highly accurate, they are computationally expensive in terms of time and resources due to their com... » read more

Introducing a Digital Engineering Methodology To Aid All Engineers


A systems engineer developing a novel system-on-a-chip (SoC) design. A CFD engineer studying the airflow over the wing of a new electric airplane design. A safety engineer reviewing the design of a new pacemaker to confirm that it is compliant with existing regulations and requirements. What do all these people have in common? One connecting thread is the ever-present need to efficiently col... » read more

Stress-Related Local Layout Effects In FinFET Technology And Device Design Sensitivity


Abstract: "Transistor characteristics in advanced technology nodes are strongly impacted by devices design and process integration choices. Variation in the layout and pattern configuration in close proximity to the device often causes undesirable sensitivities known as Local Layout Effects (LLEs). One of the sensitivities is related to carrier mobility dependence on mechanical stress, modul... » read more

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