Optimizing AI Workloads For Edge Computing


Experts At The Table: Semiconductor Engineering gathered a group of experts to discuss how some AI workloads are better suited for on-device processing to achieve consistent performance, avoid network connectivity issues, reduce cloud computing costs, and ensure privacy. The panel included Frank Ferro, group director in the Silicon Solutions Group at Cadence; Eduardo Montanez, vice president an... » read more

Chip Industry Week In Review


Breaking news: Nvidia and Synopsys announced a multi-faceted, multi-year deal that includes everything from digital twins to CUDA programming, engineering, and marketing collaboration, and Nvidia's $2B purchase of Synopsys stock. [Updated 12/1] Memory news: Micron is building a $9.6B HBM facility in the city of Higashi-Hiroshima Japan, reports Nikkei. China's ChangXin Memory Technol... » read more

Blog Review: Nov. 26


Cadence's Rajneesh Chauhan explains CXL's low power state, L0p, which maintains partial lane activity for efficient power management without compromising performance, and how comprehensive verification can help ensure reliable implementation. Siemens' John Ferguson provides a brief history of design rule checking, major advancements over the years, and why introducing it in earlier design st... » read more

AI Plays Multiple Roles Within EDA


AI's infusion into our world may seem sudden and unexpected, but EDA has been quietly adopting it for more than a decade. What's changed is that it's now becoming more visible, thanks to increasingly powerful large language models (LLMs) and the need to apply them to increasingly challenging multi-physics problems. Two fundamental shifts underlie AI's increasing prominence. First, heat is be... » read more

FPGAs Find New Workloads In The High-Speed AI Era


FPGAs are finding new applications in the age of artificial intelligence, high-speed wireless communications, medical and life science technology, and in complex chip architectures where they can improve the flow of data. Field-programmable gate arrays (FPGAs) enable designers to reprogram or reconfigure digital logic after the chips have been deployed, which is essential in the AI world, wher... » read more

The Real-World Impact Of Silicon Lifecycle Management On Chip Architectures


Silicon lifecycle management (SLM) is transforming chip architectures, empowering designers to build smarter, more resilient, and secure semiconductor devices by leveraging data from manufacturing to end of life in the field. That data can be used to improve future designs, reduce margin, and continuously optimize performance and power efficiency throughout a chip's lifetime. Moreover, under... » read more

Faster Bug Discovery And Coverage Closure


Modern chip development is a complex process where functional verification often consumes a significant portion of project time and resources. Achieving efficient bug discovery and coverage closure is essential to prevent issues from reaching silicon. This white paper introduces an innovative approach using AI-powered Verification Space Optimization (VSO.ai) to enhance verification processes. ... » read more

Chip Industry Week In Review


China's Hefei Lumiverse Technology reportedly has developed a desktop-sized High Harmonic Generation light source that generates wavelengths as small as 1nm. One customer already has used it to produce 14nm chips, which was the original target node for EUV, according to one report. As a point of comparison, TSMC and Samsung didn't start using EUV until the 7nm node, relying instead on immersion... » read more

Adding Cost, Cycle Time, And Carbon Footprint To PPA Design Targets


When engineers start designing a new semiconductor technology and fabrication process, they set targets to define what they are trying to achieve to meet the market demands and beat competitive offerings. Traditionally, they have used the metrics of power, performance, and area (PPA). This post examines how additional design targets are mandated by today’s deep submicron nodes and how develop... » read more

New Panel Production Efforts Target Interposer Costs


The rising cost of increasingly large interposers is spurring renewed interest in panel-level manufacturing, which for years has hobbled along due to the massive and collective effort required by the chip industry to change formats. Several companies are developing their own processes, although there is currently no commercial production. And a new consortium called Joint3, spearheaded by Ja... » read more

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