Building AI SoCs


Ron Lowman, strategic marketing manager at Synopsys, looks at where AI is being used and how to develop chips when the algorithms are in a state of almost constant change. That includes what moves to the edge versus the data center, how algorithms are being compressed, and what techniques are being used to speed up these chips and reduce power. https://youtu.be/d32jtdFwpcE    ... » read more

Carmakers To Chipmakers: Where’s The Data?


The integration of electronics into increasingly autonomous vehicles isn't going nearly as smoothly as the marketing literature suggests. In fact, it could take years before some of these discrepancies are resolved. The push toward full autonomy certainly hasn't slowed down, but carmakers and the electronics industry are approaching that goal from very different vantage points. Carmakers and... » read more

Blog Review: Oct. 24


Arm's Shidhartha Das digs into Power Delivery Networks with a look at how the specific roles of different components work to provide smooth supply conditions. In a video, VLSI Research's Dan Hutcheson chats with D2S CEO Aki Fujimura about the state of the photomask market, EUV optimism, and the most interesting findings from this year's eBeam Initiative survey. Synopsys' Prasad Subudhi K.... » read more

Why Invest in Automated Open Source License Management?


Software is a major component of life around us. It is at the heart of communications, transportation, safety, health, food, agriculture, defense, entertainment and virtually every other industry that one way or other touches us every day. Resourceful software development organizations and developers use a combination of previously created code, commercial software and open source software, and... » read more

Week in Review: IoT, Security, Auto


Internet of Things At Arm TechCon, Arm unveiled its Neoverse brand identity, providing an infrastructure foundation for 5G, the Internet of Things, edge computing, and other applications. The Arm Neoverse IP will proliferate next year from Arm and its technology partners. With Arm’s “Ares” platform, to be introduced in 2019, the company promises to deliver 30% per-generation performance ... » read more

Week In Review: Design, Low Power


Arm announced its new roadmap promising 30% annual system performance gains on leading edge nodes through 2021. These gains are to come from a combination of microarchitecture design to hardware, software and tools. They are branding this new roadmap 'Neoverse.' The first delivery will be Ares – expected in early 2019 – for a 7nm IP platform targeting 5G networks and next-generation cloud t... » read more

Blog Review: Oct. 17


Arm's Shidhartha Das explores the challenges of power delivery in designing mobile systems and the importance of focusing on peak power consumption. Synopsys' Meenakshy Ramachandran explains the basics of Display Stream Compression and how it works to increase the effective bandwidth enabling support of high resolution displays. Cadence's Paul McLellan shares tips on more effective market... » read more

RISC-V: More Than a Core


The open-source RISC-V instruction set architecture (ISA) is attracting a lot of attention across the semiconductor industry, but its long-term success will depend on levels of cooperation never seen before in the semiconductor industry. The big question now is how committed the industry is to RISC-V's success. The real value that RISC-V brings is the promise of an ecosystem and the opportun... » read more

Week in Review: IoT, Security, Auto


Deals Dialog Semiconductor made a blockbuster deal with Apple – the chip company will license power management technologies and transfer some assets to Apple, which will use them in their internal chip research and development. More than 300 Dialog employees, mostly engineers, will join Apple, which will pay $300 million in cash for the transaction and prepay another $300 million for Dialog ... » read more

Overcoming Low Power Verification Challenges For Mixed-Signal SoC Designs


With increasing SoC complexity and advanced power-aware architectures, a robust low power verification methodology is important for signing off the design at different stages from RTL through netlist. For mixed-signal SoCs, the challenge is, there is no well-defined low power methodology, nor are the industry’s low power verification tools equipped to handle custom designs. This article propo... » read more

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