tag: Synopsys

Tech Talk: eFPGA Timing
By Ed Sperling - 03 May, 2018 - Comments: 0

Flex Logix's Chen Wang talks about timing for an embedded FPGA and how that differs from ASIC timing. https://youtu.be/n88D1N4IEbs » read more

Connected Car Driving Defect Detection Change
By Synopsys - 02 May, 2018 - Comments: 0

Automotive product design is rapidly evolving and the magnitude and pace of change facing engineering organizations is challenging incumbent processes and resources, especially in the area of software design. While connected cars are not new, the frequency and depth to which the industry is embracing this dynamic is accelerating. Software has emerged as a primary vehicle for innovation and diff... » read more

Blog Review: May 2
By Jesse Allen - 02 May, 2018 - Comments: 0

Arm's Greg Yeric looks towards the future of 3D ICs with a dive into transistor-level 3D, including the different proposed methods of stacking transistors, power/performance benefits, and challenges such as parasitic resistance. Mentor's Kurt Takara, Chris Kwok, Dominic Lucido, and Joe Hupcey III explain how a custom synchronizer methodology can help avoid CDC mistakes and errors in FPGA des... » read more

Partitioning Becomes More Difficult
By Ann Mutschler - 30 Apr, 2018 - Comments: 0

The divide-and-conquer approach that has been the backbone of verification for decades is becoming more difficult at advanced nodes. There are more interactions from different blocks and features, more power domains, more physical effects to track, and far more complex design rules to follow. This helps explain why the number of tools required on each design—simulation, prototyping, em... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 27 Apr, 2018 - Comments: 0

Chipmakers As reported, Intel is struggling at 10nm. Intel already has encountered some difficulties, as the chip giant late last year pushed out the volume ramp of its new 10nm process from the second half of 2017 to the first part of 2018, according to analysts. Intel continues to struggle with 10nm, and has delayed the volume ramp again, according to multiple reports. During its earnings... » read more

Design Flows At 5nm And Beyond
By Mark Richards - 26 Apr, 2018 - Comments: 0

It’s probably the first time that you’ll ever hear an old (well, old-ish!) person say this, but things were easier back in my day. 40 nanometers was the most advanced node that I ever designed SoCs at and, although it wasn’t easy back then, it pales against the myriad of challenges facing designers today. Back then, compartmentalization of function and roles was relatively easy. We do ... » read more

More Nodes, New Problems
By Ann Mutschler - 26 Apr, 2018 - Comments: 0

The rollout of leading-edge process nodes is accelerating rather than slowing down, defying predictions that device scaling would begin to subside due to rising costs and the increased difficulty of developing chips at those nodes. Costs are indeed rising. So are the number of design rules, which reflect skyrocketing complexity stemming from multiple patterning, more devices on a chip, and m... » read more

Synopsys’ Vision For The New Wave Of Chip Design
By Synopsys - 25 Apr, 2018 - Comments: 0

Learn how the recent semiconductor industry shifts are breaking the traditional RTL-to-GDSII flow, and how the new Synopsys Fusion Technology helps you cross the chasm. To read more, click here. » read more

Blog Review: Apr. 25
By Jesse Allen - 25 Apr, 2018 - Comments: 0

Mentor's Cristian Filip digs into SerDes design with a focus on the adoption and evolution of Channel Operating Margin (COM) as a tool for ensuring compliance of high-speed designs and why it's useful even if its mathematical procedure might be intimidating at the beginning. Cadence's Paul McLellan explains the importance of IBIS and AMI standards for SerDes design and why the upcoming DDR5 ... » read more

The Week In Review: Design
By Jesse Allen - 20 Apr, 2018 - Comments: 0

M&A The ESD Alliance is merging with SEMI, becoming a SEMI Strategic Association Partner. SE Editor In Chief Ed Sperling argues that the merger has broad implications for the chip industry, particularly as smaller nodes require greater collaboration between design and manufacturing. Meanwhile, SEMI president and CEO Ajit Manocha explains why the combining will be of benefit to members of b... » read more

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