tag: Synopsys

Light In A Package
By Ed Sperling - 18 Sep, 2017 - Comments: 1

Silicon photonics is gaining significant traction inside the data center, but creating a simpler method of packaging the laser with other circuitry remains a stumbling block for cutting costs and using this technology across a wider swath of applications. Progress does appear to be on the horizon, even though exact time frames remain unclear. The advantages of light in communications are wel... » read more

The Week In Review: Design
By Jesse Allen - 15 Sep, 2017 - Comments: 0

Tools Cadence unveiled a new equivalence checking tool which features a massively parallel architecture capable of scaling to 100s of CPUs and adaptive proof technology that analyzes each partition and determines the optimal formal algorithm. According to the company, the Conformal Smart Logic Equivalence Checker provides an average of 4X runtime improvement with the same resources over the pr... » read more

DARPA CHIPS Program Pushes For Chiplets
By Ann Mutschler - 14 Sep, 2017 - Comments: 0

While the semiconductor industry plugs away at More Than Moore innovation, the U.S. government is guiding its own SoC development. A new program kicked off last year called ‘Common Heterogeneous Integration and IP Reuse Strategies’ or CHIPS to take its own approach the incredibly high cost of SoC design and manufacturing. DARPA said it recognizes that the explosive growth in mobile and t... » read more

CCIX – What And Why?
By Richard Solomon - 14 Sep, 2017 - Comments: 0

There are two significant issues with today’s I/O interconnects: high speed storage and networking applications need more bandwidth than currently available technologies provide, and co-processing/acceleration functions need cache coherency for faster access to memory in heterogeneous multi-processor systems. These requirements are driving the development of a new specification called Cache C... » read more

Frenzy At 10/7nm
By Ann Mutschler - 14 Sep, 2017 - Comments: 1

The number of chipmakers rushing to 10/7nm is rising, despite a slowdown in Moore's Law scaling and the increased difficulty and cost of developing chips at the most advanced nodes. How long this trend continues remains to be seen. It's likely that 7/5nm will require new manufacturing equipment, tools, materials and transistor structures. Beyond that, there is no industry-accepted roadmap, m... » read more

Functional Safety For FPGA-Based Hardware Designs
By Synopsys - 13 Sep, 2017 - Comments: 0

Advances in design and manufacturing technology allow increased factory automation, where tasks are automatically performed by sophisticated equipment such as industrial robots. Manufacturing processes require fail-safe mechanisms to prevent human injury or costly downtime. With increasing sophistication and automation of the manufacturing processes, there is increasing need for error detection... » read more

Blog Review: Sept. 13
By Jesse Allen - 13 Sep, 2017 - Comments: 0

Mentor's Andrew Macleod points to some important things to consider when beginning an automotive IC project and why differentiation, not commoditization, should be the goal. Synopsys' Amit Paunikar examines the architecture changes that make LPDDR4 faster while consuming less power. Cadence's Paul McLellan shares highlights from CDNLive Boston, from the latest in silicon photonics to how ... » read more

The Week In Review: IoT
By Jeff Dorsch - 08 Sep, 2017 - Comments: 0

Deals Deere & Co. has agreed to acquire Blue River Technology of Sunnyvale, Calif., for $305 million. The transaction is expected to close this month. Blue River develops computer vision and machine learning technology for use in precision agriculture. Monsanto Growth Ventures, Data Collective Venture Capital, Innovation Endeavors, Khosla Ventures, and Pontifax AgTech were among the investors... » read more

The Week In Review: Design
By Jesse Allen - 08 Sep, 2017 - Comments: 0

Tools Cadence unveiled an integrated memory design and verification tool, with environments for bitcell design, array and complier verification, and memory characterization. It utilizes existing simulation databases for multi-corner and Monte Carlo analysis, which the company says can lead to a 2X runtime improvement. Solido Design Automation uncorked PVTMC Verifier, which uses machine lear... » read more

The Limits Of IP Reuse
By Ed Sperling - 07 Sep, 2017 - Comments: 0

The basic business proposition for third-party IP is that it's cheaper, faster, and less problematic to buy rather than build. But things haven't exactly worked out according to plan, either for companies that license IP or those that develop it. For [getkc id="43" kc_name="IP"] licensees, just keeping track of an endless series of updates is becoming unwieldy. Complex designs often include ... » read more

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