tag: Synopsys

The Week In Review: Design
By Jesse Allen - 09 Jun, 2017 - Comments: 1

Tools Mentor added new tools to its high-level synthesis portfolio. The DesignChecks tool helps find bugs during coding with a static mode that performs very fast linting-like checks of the code and a formal mode that uses a formal engine for a more exhaustive proof of issues. The synthesis-aware Coverage tool measures code coverage for C++ signoff and fast closure of synthesized RTL. It sup... » read more

The Evolution Of Deep Learning For ADAS Applications
By Gordon Cooper - 08 Jun, 2017 - Comments: 0

Embedded vision solutions will be a key enabler for making automobiles fully autonomous. Giving an automobile a set of eyes – in the form of multiple cameras and image sensors – is a first step, but it also will be critical for the automobile to interpret content from those images and react accordingly. To accomplish this, embedded vision processors must be hardware optimized for performanc... » read more

Safety Plus Security: A New Challenge
By Brian Bailey - 08 Jun, 2017 - Comments: 0

Nobody has ever integrated safety or security features into their design just because they felt like it. Usually, successive high-profile attacks are needed to even get an industry's attention. And after that, it's not always clear how to best implement solutions or what the tradeoffs are between cost, performance, and risk versus benefit. Putting safety and security in the same basket is a ... » read more

Saving Power In A UFS Implementation Leveraging MIPI M-PHY And UniPro
By Synopsys - 07 Jun, 2017 - Comments: 0

The JEDEC Universal Flash Storage (UFS) has become the mobile storage standard of choice for today’s high-end smartphones and tablets mainly due to the specification’s performance and power advantages over other existing solutions. These advantages become critical to meet end users’ requirements for higher responsiveness and increased capabilities. For example, end users expect to transmi... » read more

Blog Review: June 7
By Jesse Allen - 07 Jun, 2017 - Comments: 0

Cadence's Paul McLellan listens in on Jeff Bier's Embedded Vision Summit keynote, where he argues the cost and power consumption of vision computing will decrease by about 1000X in the next three years. Synopsys' Sean Safarpour points to three reasons formal has grown in the last ten years to become a standard part of the verification toolbox. Mentor's Matthew Balance checks out the abili... » read more

Testing IoT Devices
By Jeff Dorsch - 05 Jun, 2017 - Comments: 3

Internet of Things devices present new challenges in testing. Some devices can be tested the same way as standard semiconductors are now tested, but others call for different approaches. Microcontrollers and other chips that go into safety-critical applications — medical devices, military/aerospace systems, and automotive electronics — need their own kind of testing to make sure they wil... » read more

The Week In Review: Design
By Jesse Allen - 02 Jun, 2017 - Comments: 0

Tools OneSpin revealed new formal applications focused on random fault verification for safety critical analysis in automotive and other mission-critical applications. The Fault Injection App provides controlled injection of faults and assertion mapping to associated fault scenarios, as well as visibility into corrupted design behavior. The Fault Detection App allows the detection of dangerous... » read more

Blog Review: May 31
By Jesse Allen - 31 May, 2017 - Comments: 0

Mentor's Michael White predicts that 10nm will come on the scene in a big way this year with a leap to an estimated 9% foundry market share. At the recent RISC-V Workshop, Cadence's Paul McLellan considers whether fully open-source silicon is really viable. Synopsys' Robert Vamosi investigates the security risks posed by the proliferation of connected aftermarket automotive products and a... » read more

The Week In Review: Design
By Jesse Allen - 26 May, 2017 - Comments: 0

Tools Startup Austemper Design unveiled a functional safety tool suite that includes safety analysis that applies default values from industry standards ISO26262 and/or IEC61508 for Failures-in-Time (FIT) rates, tools to handle safety synthesis and augment design structures, and a parallel fault simulator with hybrid simulation capabilities. SystemVerilog and VHDL parsers from Verific serve ... » read more

Verification And Validation Don’t Mean The Same Thing
By Tom De Schutter - 25 May, 2017 - Comments: 0

While often used intermixed, verification and validation are quite different procedures with different goals and different means to achieve those goals. No better way to clear up the confusion by starting with some definitions as stated by Wikipedia, https://en.wikipedia.org/wiki/Verification_and_validation: “Verification is intended to check that a product, service, or system (or porti... » read more

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