tag: Synopsys

Blog Review: August 27
By Jesse Allen - 27 Aug, 2025 - Comments: 0

Cadence's Pamula Sai Srinivas explains why clock tree synthesis is essential to ensuring that the clock signal is distributed in a way that helps achieve timing closure and maintain synchronization, performance, and reliability. Synopsys' Sajani Patel, Varun Agrawal, and Manuel Mota check out what's new in UCIe 3.0, including doubling the maximum data rate to 64 GT/s, runtime recalibration, ... » read more

Benchmark Before You Build
By Synopsys - 27 Aug, 2025 - Comments: 0

Traditional verification methods, static analysis, RTL simulation and emulation have long depended on constrained-random or targeted test suites to confirm that a design operates as intended. However, none of these approaches accurately reproduce how real users will interact with the silicon once it’s deployed in phones, datacenters, or embedded systems. To stay competitive, the semiconductor... » read more

Materials Modeling Of Superconducting Qubits In Quantum Computers
By Anders Blom - 21 Aug, 2025 - Comments: 0

While the concept of quantum computing has been discussed for more than 40 years, only recently have experiments indicated that a practical quantum computer may be possible. Recent developments in this area have captured headlines with dramatic claims—and equally dramatic rebuttals. Google’s Willow chip demonstrated error-corrected operations in late 2024, while D-Wave’s assertion of quan... » read more

Manufacturing At The Limits
By Gregory Haley - 21 Aug, 2025 - Comments: 2

Hybrid bonding has been in production for several years, with mature flows capable of delivering robust yields using 10µm interconnects. At that scale, processes can tolerate hundreds of nanometers of overlay variation, modest differences in wafer bow, and particle sizes rivaling the interconnect height without catastrophic impact. Hybrid bonding is compatible with optical metrology, existing ... » read more

Reticle Stitching Bumps Up Silicon Interposer Costs
By Bryon Moyer - 21 Aug, 2025 - Comments: 0

Advanced packaging often relies on silicon interposers to connect chiplets and other components inside a package. The problem is that interposers typically exceed the reticle limit, which adds both complexity and cost. An interposer is essential for 2.5D and 3.5D architectures. As device scaling runs out of steam, chipmakers are decomposing planar SoCs into chiplets and connecting them throu... » read more

Blog Review: August 20
By Jesse Allen - 20 Aug, 2025 - Comments: 0

Cadence's Sriram Sharma Kalluri finds that time-of-flight sensors are poised to revolutionize ADAS by generating precise 3D point clouds that, particularly when combined with lidar, contribute to an exceptionally accurate and comprehensive understanding of the vehicle's surroundings. Synopsys' Igor Markov and other industry experts discuss how quantum computing is moving from research to p... » read more

Best Options For Using AI In Chip Design
By Ed Sperling - 20 Aug, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss how and where AI can be applied to chip design to maximize its value, and how that will impact the design process, with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at S... » read more

Complex Mix Of Processors At The Edge
By Liz Allan - 18 Aug, 2025 - Comments: 1

With AI changing so fast, it’s a juggle for companies to ensure they can deliver the best performance now while also future-proofing for unknown AI models or a completely different approach to training and inference that may emerge. There are a slew of options for high-end and budget phones, hyperscalers, and low-cost, low-power edge devices, and while GPUs keep making headlines, many designe... » read more

Chip Industry Week in Review
By The SE Staff - 15 Aug, 2025 - Comments: 0

Lines are blurring between government and industry: On the heels of last week's resignation demand, Intel CEO Lip-Bu Tan met with President Trump on Monday, with the President later saying, "The meeting was a very interesting one. His success and rise is an amazing story."  Now, Bloomberg reports the Trump administration is in talks with Intel for the U.S. government to take a stake in th... » read more

System-Level Design For 1.6 Tbps Interoperability In AI Data Centers
By Madhumita Sanyal - 14 Aug, 2025 - Comments: 0

By Madhumita Sanyal and Diwakar Kumaraswamy The rapid escalation of AI/ML workloads—driven by increasingly large language models—is reshaping high-performance computing and AI data center architectures. Real-time inference and large-scale training are pushing the limits of compute and interconnect performance. With model sizes and parameter counts doubling every 4–6 months, infrastruct... » read more

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