Security Requirements And Penalties Grow For Chipmakers


Governments and systems companies are fundamentally changing the rules around semiconductor security, forcing chipmakers and their suppliers to comply with tough new regulations that require resiliency in hardware. Unlike in the past, chips and systems deployed in these markets must be able to respond to threats rather than waiting for the next version of a chip or IP to address vulnerabilities... » read more

The Criticality of Performance per Watt Optimization for AI Chip Development


Chip developers are seeing an urgent rise in demand for compute processing capability driven by AI workloads. This increase in compute requirements drives a corresponding increase in the demand for power consumption. For example, a ChatGPT query requires nearly 10 times as much power, on average, as a Google search. Power has traditionally been treated as a secondary constraint, with perform... » read more

Blog Review: September 3


Cadence's Sriram Sharma Kalluri compares convolutional neural networks (CNNs) and transformers to show how their different architectures give them particular strengths and why the choice between them depends on the specific task, the available data, and the computational resources. Siemens' John McMillan provides a primer on the major IC package types, how they influence system design, therm... » read more

AI’s Value In Chip Design Depends On Data Availability


Experts at the Table: Semiconductor Engineering sat down to discuss the advantages and challenges in using AI in designing chips, with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at Synopsys; Sailesh Kumar, CEO of Baya Systems; Mehir ... » read more

Chip Industry Week in Review


Microsoft, OpenAI, and NVIDIA warned about power swings and physical damage to power grids increasing from AI training workloads and jointly proposed a multi-pronged approach to stabilize power in AI training data centers. Meanwhile, Anthropic issued a warning about the weaponization of agentic AI in a new 25-page Threat Intelligence report. Key concerns involve the evolution in AI-assisted ... » read more

Chiplet Design Considerations


Chiplets are a way to offer continuing increases in compute capacity and I/O bandwidth needs by splitting SoC functionality into smaller heterogeneous or homogeneous dies called chiplets and integrating these chiplets into a single system in package (SIP), where the total silicon content can exceed the reticle size of a single SoC. SIP includes traditional package substrates but also may includ... » read more

Government Funding For Chip Design Tools Spreads


Governments around the globe are starting to invest more heavily in chip design tools and related research as part of an effort to boost on-shore chip production, opening new opportunities for startups and established EDA companies. Those cash infusions, which are being doled out in the U.S., Europe, and Asia, are part of a growing recognition of the importance of design automation tools wit... » read more

Silicon Lifecycle Management Gains Traction, But It’s Complicated


Silicon lifecycle management (SLM) is gaining ground in semiconductor design and test by leveraging specialized on-die sensors and analytics engines to improve power, performance, yield, and reliability. Most modern SoCs mitigate the guesswork by leveraging DFT, which includes adding memory built-in self-test (BiST) or improving functional coverage, but these tests were meant for verifying c... » read more

Verification Fails To Keep Up


Experts at the table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight; Gor... » read more

Physical Access Control Raises New Security Concerns


Experts At The Table: Semiconductor Engineering sat down to discuss hardware security challenges, including fundamental security of GenAI, with Nicole Fern, principal security analyst at Keysight; Serge Leef, AI-For-Silicon strategist at Microsoft; Scott Best, senior director for silicon security products at Rambus; Lee Harrison, director of Tessent Automotive IC Solutions at Siemens EDA; Mohit... » read more

← Older posts Newer posts →