tag: Synopsys

The Week In Review: Design/IoT
By Jesse Allen - 01 May, 2015 - Comments: 0

Tools Cadence released the new debug platform Indago, with the aim of reducing the time to identify bugs in a design by up to 50 percent compared to traditional signal- or transaction-level debug methods. Included are three debugging apps that provide an integrated debug solution for testbench, verification IP, and hardware/software debug for SoC designs. Mentor Graphics announced three n... » read more

FD-SOI Vs. FinFETs
By Ed Sperling - 30 Apr, 2015 - Comments: 0

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

Blog Review: April 29
By Jesse Allen - 29 Apr, 2015 - Comments: 0

Start your engines. At the Western US Freescale Cup, ARM's Sadanand Gulwadi had a front-row seat to the ingenuity displayed in autonomous model car racing. From turning an abandoned factory into the world's largest indoor farm to the millions invested in mining passing asteroids, Ansys' Bill Vandermark celebrates a week of Earth Day with his top five picks to read. "There is no Department... » read more

The Week In Review: Design/IoT
By Jesse Allen - 24 Apr, 2015 - Comments: 0

Mergers & Acquisitions Synopsys continued expansion into the software security market with the acquisition of Codenomicon. The Finnish company was in the headlines this time last year when it discovered the Heartbleed bug during product testing. Tools Mentor Graphics released Calibre xACT, a parasitic extraction platform which automatically optimizes extraction techniques based on ... » read more

What EDA’s Big 3 Think Now
By Ed Sperling - 23 Apr, 2015 - Comments: 0

In the past two months the CEOs of Cadence, Synopsys and Mentor Graphics delivered their annual high-level messages to their respective user groups. Semiconductor Engineering attended all of the speeches at these conferences, as it did in 2014 (see story here). From a high level, the big issues for CEOs last year were Moore's Law, the costs of design, the impact of low power, and business-... » read more

Is Art Acceptable In Verification?
By Brian Bailey - 23 Apr, 2015 - Comments: 0

The industry appears to have accepted that [getkc id="10" kc_name="verification"] involves art as well as science. This is usually based on one of three reasons, namely: the problem is large and complex; there is a lack of understanding and tools that enable it to be automated; and if it could be made a science, all of the jobs would have migrated offshore. Today, designs are built from pre-... » read more

Pressure Builds To Revamp The Design Flow
By Ed Sperling - 23 Apr, 2015 - Comments: 1

Without [getkc id="7" kc_name="EDA"] there would be no [getkc id="74" comment="Moore's Law"] as we know it today, and without Moore's Law there would be a much more limited need for EDA. But after more than three decades of developing design flows packed with sophisticated tools to automate semiconductor design through verification, and thereby enable feature shrinks that are the basis of Moore... » read more

Blurring The Lines On Prototyping
By Ann Mutschler - 23 Apr, 2015 - Comments: 0

Prototyping is an integral part of every [getkc id="81" kc_name="SoC"] today, with two main approaches being used: virtual or software-based, and physical, which includes FPGA-based boards as well as hardware emulation systems. [getkc id="104" kc_name="Virtual prototyping"] is typically used for software development in the early stages of SoC design, even before SoC [getkc id="49" kc_name="R... » read more

Accelerate IP Software Development With Virtual Prototypes
By Tom De Schutter - 23 Apr, 2015 - Comments: 0

Almost all electronics devices have some way to connect to other devices. While we don’t really think about it a lot, these interfaces actually have to be quite smart and need to deal with a lot of different device types and/or handle a great deal of data, preferably all while consuming as little power as possible. As a result, device drivers for this type of interface IP are non-trivial.... » read more

Layering Protocol Verification
By Synopsys - 22 Apr, 2015 - Comments: 0

Layering protocols are modeled using layering structures that mirror the protocol layers. There are significant challenges in modelling verification components for layering protocols such as (1) reuse, (2) scalability, (3) controllability, and (4)observability. Furthermore, there may be requirements for complex test scenarios where a great deal of interaction is required between test sequence e... » read more

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