tag: Synopsys

Halloween Is Going Mobile
By Tom De Schutter - 24 Oct, 2013 - Comments: 0

With the end of October around the corner, my children are frantically thinking about what they want to dress up as for Halloween. It is interesting that both of them chose a costume that has something to do with a mobile video game. My daughter will be dressing up as a red angry bird while my son wants to go as a wizard, where he is using clash of clans as the example of what a wizard should l... » read more

Start Verification Early To Avoid Pitfalls Later
By Ann Mutschler - 24 Oct, 2013 - Comments: 1

It is well understood – at least from a theoretical point of view – that design verification should start as early as possible. The reality is that that doesn’t always happen for a variety of reasons such as enormous time to market pressure, too many new features to add, lack of foresight and discipline among other things. But progress is being made. Harry Foster, chief scientist for v... » read more

Virtual Prototypes For Early Software Development
By Various Writers - 24 Oct, 2013 - Comments: 0

In previous white papers, we've looked at the demands of the rapidly changing market and how the use of virtual prototypes has evolved to help meet them. In this white paper, we look specifically at the challenges of developing some of the hardware-dependent software layers - namely boot ROM code, OS bring-up, driver development - used in fast-evolving mobile devices and how to use virtual prot... » read more

Experts At The Table: Debug
By Ed Sperling - 18 Oct, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: The amount of IP is increasing and i... » read more

The Week In Review: Oct. 18
By Mark LaPedus - 18 Oct, 2013 - Comments: 0

By Mark LaPedus & Ed Sperling The problems continue with extreme ultraviolet (EUV) lithography. ASML promised to deliver an 80 Watt power source by year’s end. Now, the company said it only will have a 70 Watt source by mid-2014. “We are focusing on reaching the 70 Watts by the middle of next year,” said Peter Wennink, ASML’s CEO, in a conference call to discuss the company’s res... » read more

Blog Review: Oct. 16
By Ed Sperling - 16 Oct, 2013 - Comments: 0

Cadence’s Richard Goering follows Si2’s move into SPICE modeling following the acquisition of the Compact Model Council. Combining standards groups is a growing trend these days. Mentor’s Colin Walls points to the demise of reset buttons. You can always trip a circuit breaker, and usually turn off a device by pulling out the battery, but a reset button is simpler. Where did they go? ... » read more

The Brave New World Of FinFETs
By Ed Sperling - 10 Oct, 2013 - Comments: 0

SoCs using 16nm and 14nm finFETs are expected to begin rolling out next year using a 20nm back-end-of-line process. While the initial performance and power numbers are looking very promising, the challenges of designing and building these complex chips are daunting—and there are more problems on the way. First, the good news. Initial results from foundries show a 150% improvement in perfor... » read more

Transient Current Crunch
By Ann Mutschler - 10 Oct, 2013 - Comments: 0

When Intel talks, people listen. So when Intel executive VP Dadi Perlmutter said in a keynote at ISSCC in 2012 that transient power noise was one of the most limiting aspects of the chip design process—and how the package and the board inductance are limiting how low they can take the supply voltage—it showed the gravity of the challenge of effectively managing transient power. Transient po... » read more

On-Chip MCUs Excel At Power Management
By Ann Mutschler - 10 Oct, 2013 - Comments: 0

By Ann Steffora Mutschler When it comes to supplying power to an SoC, there is an increasing trend to make it more intelligent—how to control it more accurately, how it is monitored and how it communicates with different aspects of the chip. Traditional power supply models with analog supplies have less of this control, so a number of engineering teams are considering the use of on-chip m... » read more

Experts At The Table: Who Takes Responsibility?
By Ed Sperling - 10 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down with John Koeter, vice president of marketing and AEs for IP and systems at Synopsys; Mike Stellfox, technical leader of the verification solutions architecture team at Cadence; Laurent Moll, CTO at Arteris; Gino Skulick, vice president and general manager of the SDMS business unit at eSilicon; Mike Gianfagna, vice president of corporate marketing at Atrenta; ... » read more

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