tag: Synopsys

Low Power Verification – “X” Marks the Spot
By David Hsu - 10 Oct, 2013 - Comments: 1

Welcome to a new discussion on a range of topics we think will be interesting to folks who design and verify SoCs. Though the name of this blog denotes two top attributes of SoCs—IP implementation and the pervasive need for low power (LP), we certainly may go far beyond the scope of these topics in upcoming posts. We’ll start with a topic on the LP side, and going forward we’ll alternate ... » read more

Flexibility Improves Memory Interface Bandwidth
By Ann Mutschler - 10 Oct, 2013 - Comments: 0

In today’s SoCs, memory is the heart or at least one of the main elements of the design. As such, designing them carefully is paramount to achieving the best bandwidth, performance and power. Performance is very important to be able to access the memory and to trade and store information from different IPs with shared memories or local memories. From the power perspective, every access to... » read more

Advanced Verification IP Accelerates PCIe Integration Test
By Various Writers - 10 Oct, 2013 - Comments: 0

System-on-chip (SoC) complexity is being driven by platform convergence and the need for more processing power and lower power consumption. The complexity of SoC standards-based interfaces has similarly increased for the same reasons: low power, improved quality of service and high throughput. Design teams have adopted IP and reuse for designs of these complex protocols so they can focus their ... » read more

Blog Review: Oct. 9
By Ed Sperling - 09 Oct, 2013 - Comments: 0

By Ed Sperling Mentor’s Simon Favre raises an interesting question: Why are 450mm wafers and EUV lithography related? The answer may surprise you. In his second broadcast, Cadence’s Brian Fuller interviews Gary Smith about where EDA will grow, why industry consolidation is a myth and why there is a dearth of reliable information about the electronics industry. Synopsys’ Mick Posner... » read more

The Week In Review: Oct. 4
By Mark LaPedus - 04 Oct, 2013 - Comments: 0

By Mark LaPedus & Ed Sperling eSilicon introduced an automated multi-project wafer quote system, which allows companies to sort through a number of options and get pricing. The quotes are tied into TSMC's 20nm to 350nm processes, and GlobalFoundries’ 20nm to 180nm processes. The approach eliminates the need for companies to buy a full wafer if their volume requirements don’t warrant it... » read more

Blog Review: Oct. 3
By Ed Sperling - 03 Oct, 2013 - Comments: 0

Cadence’s Brian Fuller rolls out a twice-monthly TV program called “Unhinged,” which he bills as a cross between The Daily Show, Letterman and ESPN. The intro is a classic. Who needs coffee? Synopsys’ Karen Bartleson interviews Bob Metcalfe, co-inventor of Ethernet, creator of Metcalfe’s Law—which has withstood the test of time quite well—on why Ethernet still really important.... » read more

Why does EUV matter?
By Brian Bailey - 01 Oct, 2013 - Comments: 0

By Brian Bailey The end of Moore’s Law has been predicted for almost as long as the law has existed. It normally comes down to some great technological barrier that cannot be breached, only to find that a solution is just around the corner and the concerns fade until the next barrier is identified. At DAC this year (2013), there were many predictions about why Moore’s Law will end in th... » read more

The Week In Review: Sept. 27
By Ed Sperling - 27 Sep, 2013 - Comments: 0

By Ed Sperling Applied Materials shook up the equipment market, announcing a deal to buy Tokyo Electron for about $9.3 billion in stock. The combination of No. 2 Applied and No. 3 TEL in that market equals a new No. 1, surpassing Dutch giant ASML in terms of revenue. Mentor Graphics rolled out a new versiion of its computational fluid dynamics product, adding Monte Carlo radiation modeling... » read more

Buying And Selling EDA Companies
By Ed Sperling - 26 Sep, 2013 - Comments: 0

By Ed Sperling Buying companies is the easy part. Integrating them is the hard part. It’s also the point where most acquisitions that go awry actually run into problems. There are widely different strategies for how to accomplish integration. Sometimes they work, other times they don’t. And sometimes both companies are surprised by the outcome—for better or worse. “Either you thi... » read more

Established Nodes White Paper
By Various Writers - 26 Sep, 2013 - Comments: 0

A look at advanced place and route design for established process nodes. To download this white paper, click here. » read more

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