tag: Synopsys

A Tale Of Two Standards
By Ed Sperling - 18 Jul, 2013 - Comments: 0

By Ed Sperling It could well be one of the strangest developments in standards history. Two competing standards for power formats were rolled out in the middle of the last decade and aside from a few cries of foul they fell below the radar screen of most chip designers and architects for a half-dozen years. Fast forward to the present and the Common Power Format (CPF) and Unified Power Form... » read more

Experts At The Table: Changes In The Ecosystem
By Ed Sperling - 15 Jul, 2013 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael Buehler-Garcia, director of design solutions marketing at Mentor Graphics; Seow Yin Lim, group director for marketing at Cadence; Kevin Kranen, director of strategic alliances at Synopsys, and Tom Quan, director at TSMC. What follows are excerpts of that conversation. SMD: Does the increasing collaboration in the ecos... » read more

Experts At The Table: SoC Prototyping
By Ann Mutschler - 12 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss SoC prototyping with Hillel Miller, pre-silicon verification/emulation manager at Freescale Semiconductor; Frank Schirrmeister, group director, product marketing, system development suite at Cadence; and Mick Posner, director of product marketing at Synopsys. What follows are excerpts of that conversation. SLD: Is it possib... » read more

Software Debug Gets Tricky
By Ann Mutschler - 11 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler As designs continue to grow in size and complexity, that complexity has led to an increasing number of processing cores. Additional cores, in turn, allow for additional software to be run on those cores, and debugging the software becomes critical. Traditionally, emulation has played a significant role in verifying that software against RTL code, and continues to d... » read more

Dealing With New Bottlenecks
By Ed Sperling - 11 Jul, 2013 - Comments: 0

By Ed Sperling While the number of options for improving efficiency and performance in designs continues to increase, the number of challenges in getting chips at advanced process nodes out the door is increasing, too. Thinner wires, routing congestion, more power domains, IP integration and lithography issues are conspiring to make design much more difficult than in the past. So why aren�... » read more

The Controversial Spec
By Ann Mutschler - 11 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler Design sophistication and complexity has made it increasingly difficult to fully specify the expected behavior of a block in an SoC, but this is necessary for design and verification teams. How do you write a “good” and “complete” specification of functionality? It turns out that the discussion of defining what a good and complete specification is and how t... » read more

MacBook Air 2013: Power Efficient To The Core(s)
By Synopsys - 11 Jul, 2013 - Comments: 0

By Cary Chin Last month, we looked at the initial announcement at WWDC of the latest MacBook Air laptops. These new machines are physically nearly identical to their predecessors, boast negligible performance improvements (and even performance degradation in some instances), cost about the same, and yet in my view are perhaps the most revolutionary products since the MacBook Air line was reinv... » read more

The Rise Of Semiconductor IP Subsystems
By Various Writers - 11 Jul, 2013 - Comments: 0

The semiconductor IP (SIP) market arose when SIP vendors created IP functions that mirrored those found in the discrete semiconductor market and made those functions available to SoC designers in the form of hard or soft SIP blocks. As the SoC and SIP markets evolved, it was a natural evolution that many discrete SIP functions be converged into larger blocks that mimic system-level functions (i... » read more

Blog Review: July 10
By Ed Sperling - 10 Jul, 2013 - Comments: 0

By Ed Sperling Mentor’s Harry Foster rolls out part four of his epic functional verification study, this one on design and verification reuse. If you work in the verification world, pounce. Cadence’s Brian Fuller looks back over a quarter century of technology—and what the average salary of a hardware design engineer will be in a 15 years: $499,000. But what will a cup of coffee cost?... » read more

Experts At The Table: Changes In The Ecosystem
By Ed Sperling - 01 Jul, 2013 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael Buehler-Garcia, director of design solutions marketing at Mentor Graphics; Seow Yin Lim, group director for marketing at Cadence; Kevin Kranen, director of strategic alliances at Synopsys, and Tom Quan, director at TSMC. What follows are excerpts of that conversation. SMD: How are chipmakers working with the rest ... » read more

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