tag: Synopsys

Design Topology Requires Physical Data
By Ann Mutschler - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler To best understand a design topology and make decisions on clock/register gating, vector sets are required for the RTL tools to understand how to gate clocks and registers. However, if certain constraints are set on all enabled signals in RTL they can be re-used for gating clocks and registers downstream where enablers are not available—even without needing a ... » read more

Reducing Wait Time
By Tom De Schutter - 25 Apr, 2013 - Comments: 0

By Tom De Schutter Last month we were all waiting for white smoke to emerge from the chimney on the roof of the Sistine Chapel at the Vatican. I am of course talking about the election of the new pope. I couldn’t help but see a parallel with how software developers are anxiously waiting for their software to run correctly and finally get past the series of seemingly never ending bugs (black ... » read more

Virtual Prototypes: When, Where And How To Use Them
By Various Writers - 25 Apr, 2013 - Comments: 0

An innovation-hungry public and a highly competitive marketplace make for short product cycles, while the sophistication and performance expected of digital devices grows with every new product generation. Heterogeneous multiprocessing, where different cores do specialized work, has become the industry norm inside those devices, radically increasing the amount of software needed, the importance... » read more

Experts At The Table: Verification Nightmares
By Ed Sperling - 23 Apr, 2013 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Shabtay Matalon, ESL marketing manager in Mentor Graphics’ Design Creation Division; Bill Neifert, CTO at Carbon Design Systems; Terrill Moore, CEO of MCCI Corp., and Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys. What follows are excerpts of that conversation. LPE: Where does power fit in? N... » read more

Subsystems And Reuse
By Frank Schirrmeister - 23 Apr, 2013 - Comments: 0

By Frank Schirrmeister The last couple of weeks have been very busy with travel, customer meetings and presentations—DATE in Grenoble, CDNLive in San Jose and, most recently, EDPS in Monterey. Software enablement and IP sub-systems have been the key themes throughout these events, and during Gary Smith’s keynote at EDPS, I realized that subsystem reuse may be a significant step to solving ... » read more

Experts At The Table: FinFET Questions And Issues
By Ed Sperling - 19 Apr, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the current state and future promise of finFETs, and the myriad challenges, with Ruggero Castagnetti, an LSI fellow; Barry Pangrle, senior power methodology engineer at Nvidia; Steve Carlson, group director of marketing at Cadence; and Mary Ann White, director of product marketing at Synopsys. What follows are excerpts o... » read more

Fixing DP Errors: Colors Or Rings
By Ann Mutschler - 18 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler With the move to the 20nm manufacturing node, double patterning (DP) became a requirement. In addition, topology changes occurred that demanded very regular structures, marking a significant departure from 28nm design. As a result of this new approach, new errors are popping up, such as DP violation loops, odd cycle violations and anchor path violations. Certain... » read more

Optimizing IP For Power
By Ed Sperling - 11 Apr, 2013 - Comments: 0

By Ed Sperling As the amount of commercial IP in an SoC increases, the entire bill of materials is coming under increasing scrutiny because of a new concern—power. Commercial IP, after all, is largely a collection of black-box solutions to speed up the time it takes to bring a chip to market, and frequently to improve the quality, but the cumulative impact on the system power budget has neve... » read more

Dangerous Electricity
By Ann Mutschler - 11 Apr, 2013 - Comments: 0

Electricity to the modern age is as indispensible as air, but too much can be a bad thing for automotive and aerospace applications—especially when it is in the form of electrostatic discharge (ESD). As chips advance to 28nm, 20nm and 16nm, the design window for electrostatic discharge is shrinking for a number of reasons, explained Norman Chang is vice president and senior product strategis... » read more

The Power Game
By Ann Mutschler - 11 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler Semiconductor engineering teams always have focused on stepping up performance in new designs, but in the mobile, GPU and tablet markets they’re finding that maintaining the balance between higher performance and the same or lower power is increasingly onerous. The reason: Extreme gaming applications can create scenario files that cause dynamic power consumpt... » read more

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