tag: Synopsys

The Growing Integration Challenge
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ed Sperling As the number of processors and the amount of memory and IP on a chip continues to skyrocket, so does the challenge for integrating all of this stuff on a single die—or even multiple dies in the same package. There are a number of reasons why it’s getting more difficult to make all of these IP blocks work together. First of all, nothing ever stands still in design. As a r... » read more

New Incentives For Lowering Power
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ed Sperling Despite all the focus by design teams on lowering power over the past few years, in many applications power is still the last consideration for many companies in the power-performance-area equation. That’s beginning to change, however, even for applications that in the past have not been particularly power-sensitive. There are several reasons for this shift. No. 1 on the li... » read more

iPad Mini: The iPad On A diet
By Synopsys - 08 Nov, 2012 - Comments: 0

By Cary Chin The iPad mini was unveiled last month, but just hit the stores on Nov. 2. Early reviews have been quite positive—good performance, quality build, excellent battery life. There’s just one problem (besides the price)—the non-retina display. Even with a 1024 x 768 display (the same resolution as the original iPad and iPad 2), it seems we’ve gone “retina display” mad, and ... » read more

The New Mixed-Signal Flow
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler We are on the cusp of the mixed-signal era. Traditional mixed-signal design environments, in which analog and digital parts are implemented separately, no longer are sufficient. They lead to excess iteration and prolonged design cycle time. Today’s mixed-signal designs require a new approach that enables design teams to be as efficient as possible productivity... » read more

The Growing Confidence Gap In Verification
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ed Sperling It’s no surprise that verification is getting more difficult at each new process node. What’s less obvious is just how deep into organizations the job of verifying SoCs and ASICs now extends. Functional verification used to be a well-defined job at the back end of the design flow. It has evolved into a multi-dimensional, multi-group challenge, beginning at the earliest st... » read more

Calculating Emulation’s Complex Cost Of Ownership
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler Hardware emulation or hardware-assisted verification –whichever term you choose—has been around for decades. But until recently it has seen only modest adoption due to the high cost, long set-up time, power and IT requirements, among other things. But with simulation running out of steam between 50 and 100 million gates, this specialized hardware makes a ... » read more

Making Important Choices
By Nithya Ruff - 25 Oct, 2012 - Comments: 0

By Nithya Ruff Last year, my daughter was a senior in high school, very busy finalizing her college selections and completing college applications. For anyone who has gone through this recently, it is not a trivial task to select a place where you will spend the next four years, a place that will shape your future and where you will be spending a good amount of your parent’s money. This expe... » read more

Design Solutions For 20nm And Beyond
By Various Writers - 25 Oct, 2012 - Comments: 0

The consumer’s insatiable demand for greater performance, a shrinking form factor and extended battery life, all while continuing the trend for lower end user cost is the driving force behind the semiconductor industry’s rapid evolution to ever smaller process geometries. As with many of the previous process geometry shrinks, there will be the usual concerns about the increase in design ... » read more

Experts At The Table: The Business Of IP
By Ed Sperling - 19 Oct, 2012 - Comments: 0

Low-Power/High-Performance Engineering sat down to discuss IP supply chain issues with Jim Hogan, an independent VC; Jack Brown, senior vice president at Sonics; Mike Gianfagna, vice president of marketing at Atrenta; Paul Hollingworth, vice president of strategic accounts at eSilicon, and Warren Savage, CEO of IPextreme. What follows are excerpts of that conversation. LPHP: There’s so muc... » read more

Experts At The Table: The Sky Isn’t Falling
By Ann Mutschler - 18 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler SemiMD sat down recently to discuss how the industry is making 3D ICs a reality today with Sylvan Kaiser, chief technology officer at Docea Power; Steve Smith, senior director for 3D-IC strategy at Synopsys; and Dr. Ahmed Jerraya, director of strategic design programs at CEA-LETI. For part one of this series, click here. SemiMD: Because CEA-LETI has direct expe... » read more

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