tag: Synopsys

The New Frontier: Low-Power Verification And Test
By Ed Sperling - 09 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler By now there’s no argument that verification and test strategies must be considered at the very earliest stages of any design cycle, and when it comes to low-power designs, the advanced techniques used and design complexity make the challenges here even more daunting. Low-power verification and test strategies have been in development for a number of years, and it... » read more

The Rise Of The Power Architect
By Ed Sperling - 09 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler Call them power czars, power gurus or power architects, this role within design teams is gaining importance with the need to understand, manage and control the power budget throughout the entire design process. As such, power architects are in high demand today with power architecture teams doubling in size within a year or two. Driving the need for this highly s... » read more

Routing Congestion Returns
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling Routing congestion has returned with a vengeance to SoC design, fueled by the advent of more third-party IP, more memory, a variety of new features, as well as the inability to scale wires at the same rate as transistors. This is certainly not a foreign concept for IC design. The markets for place and route tools were driven largely by the need to automate this kind of operat... » read more

SoC Platforms Gain Steam
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling Platforms are attracting far more attention from makers of SoCs because they are pre-verified and can speed time to market, but the shift isn’t so simple. It will spark major changes in the way companies design and build chips, causing significant disruption across the entire SoC ecosystem. Platforms are nothing new in the processor and software world. Intel, IBM AMD, and N... » read more

printf(“I Like”);
By Achim Nohl - 26 Jul, 2012 - Comments: 0

By Achim Nohl Debugging software by adding printf statements in the code is not considered the cleanest and most advanced debugging approach, but when you are searching for the root cause of a problem you often look to the debugging method you are most familiar with and can apply easily. The hurdle of setting up a complex debug or trace tool is counterproductive when dealing with schedule c... » read more

Multi-Source CTS Delivers Flexible High Performance and Variation Tolerance
By Various Writers - 26 Jul, 2012 - Comments: 0

Multi-source clock tree is a hybrid containing the best aspects of a conventional clock tree and a pure clock mesh. This paper illustrates the benefits such as lower skew and better on-chip-variation (OCV) performance compared to a conventional clock tree. To download this white paper, click here. » read more

Bridging The Rift Between Software And Hardware
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ed Sperling As more computing is done on mobile devices rather than desktops, the idea of what constitutes good application software is changing. This addresses the key reason why some of advanced power-saving features built into chips were not utilized by software in the past. Unless the operating systems were specifically written for mobile devices, such as Android and iOS, the real f... » read more

Executive Briefing: The Next Five Years
By Ed Sperling - 12 Jul, 2012 - Comments: 0

Low-Power/High-Performance Engineering talks with Synopsys CEO Aart de Geus about what's changing in design, the role of hardware and software, and what comes next. [youtube vid=RxDGmKRBbPQ] » read more

Experts At The Table: Pain Points
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: Where will the pain points be going forward? Kariat: 20nm is... » read more

Experts At The Table: Improving The Efficiency Of Software
By Ed Sperling - 29 Jun, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Design sat down to talk about how to write better software with Jan Rabaey, Donald O. Pederson Distinguished Professor at the University of California at Berkeley; Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Emily Shriver, research scientist at Intel; Alan Gibbons, principal engineer at Synopsys; and Dav... » read more

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