SEMICON Taiwan’s Packaging Punch


SEMICON Taiwan packed a punch, setting several new records and new heights in 2015. This year marked the 20th anniversary of SEMICON in Taiwan and was the largest SEMICON in Taiwan ever, with a Nobel Prize winner (Professor Shuji Nakamura, 2014’s winner) keynoting the Executive Summit, Taiwan’s President Ma speaking at the hugely attended Gala Dinner, and 2015 on track for TSMC to be the wo... » read more

Brite Semiconductor: Design Services


These days it's increasingly common for large commercial foundries to have a design services counterpart—TSMC has GlobalUnichip. GlobalFoundries has an entire ecosystem as well as a dedicated partner, Invecas. And China's SMIC has Brite Semiconductor. Brite was founded in 2008 by Open-Silicon as a way to tap the Chinese market, but the startup has taken some twists since then. It now is un... » read more

How To Test IoT Devices


At a recent event, test experts said the IC industry needs a new paradigm in testing chips for the [getkc id="76" comment="Internet of Things"] (IoT). The message was fairly simple to interpret. Existing automatic test equipment (ATE) is well suited to test today’s digital, analog, and mixed-signal chips, though it may be ill-equipped or too expensive to test IoT-based devices. But wha... » read more

Stacked Die Are Coming Soon. Really


Since the beginning of the decade there have been many predictions that stacked die were just over the hill, but the time it has taken to climb that hill has been longer than most people would have anticipated. In fact, TSMC has been fully capable of building stacked die since last year, with risk production expected to be completed by year, according to Gartner. But something very fundament... » read more

Semicon West Preview: Packaging


By Paula Doe The evolving mobile device market means the packaging, assembly and test supply chain faces a growing range of alternative technologies vying for its investment dollar, everything from Google’s modular electronics with 3D printing, to more solutions for integrating varied chips in smaller packaged systems. One potentially disruptive change is the wider use of more open-source... » read more

The Rise Of Semiconductor IP Subsystems


The semiconductor IP (SIP) market arose when SIP vendors created IP functions that mirrored those found in the discrete semiconductor market and made those functions available to SoC designers in the form of hard or soft SIP blocks. As the SoC and SIP markets evolved, it was a natural evolution that many discrete SIP functions be converged into larger blocks that mimic system-level functions (i... » read more

What’s Ahead For System-Level Design


By Ann Steffora Mutschler Architecting an SoC today is incredibly difficult. When you add in the number of available transistors, the manufacturing effects of smaller nodes, IP and software that must be integrated, among other things, the challenges just keep mounting. Depending on what market segment the SoC will be designed into has a huge impact, as well. “It is impossible to ove... » read more

What’s Before Stacked Die?


By Mark LaPedus Advanced 2.5D/3D chip stacking has a number of challenges and is still a few years away from mass production. In fact, mass production may not occur until 2015 or 2016. But OEMs can ill afford to sit still and wait for 2.5D/3D technology to mature. So, until 2.5D/3D is ready for prime time, chipmakers and IC-packaging houses are under pressure to innovate and extend current ... » read more

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