tag: TSMC

Why the Big Players Like 450mm Wafers
By Chris Mack - 20 Aug, 2012 - Comments: 0

The reason semiconductor manufacturers like the idea of 450-mm wafers is easy to understand:  bigger wafers should lower the per-chip cost of manufacturing.  But as I mentioned in my last post, this per-chip cost advantage doesn’t apply to lithography.  Each time a wafer size is increased, only the non-litho (per-chip) costs go down, and so lithography costs take up a bigger portion of the... » read more

The Trouble With FinFETs
By Joanne Itow - 16 Aug, 2012 - Comments: 0

By Joanne Itow The industry’s quest to continue on the semiconductor roadmap defined by Moore’s Law has led to the adoption of a new transistor structure. Whether you call them finFETs, tri-gate or 3D transistors, building these new devices is difficult. But the technology is only half the challenge. In 2002, Chen Ming Hu* spoke at the Semico Summit. The title of his presentation was �... » read more

G450C To Align Vendors During 450mm Transition
By Ed Sperling - 16 Aug, 2012 - Comments: 0

By David Lammers Innovation and synchronization among multiple companies do not often go hand in hand. But for the 450mm wafer transition to provide its full benefits, chip makers and their suppliers will need to do more than a simple wafer size scale up. That may lead the Global 450 Consortium (G450C) to serve as the proving ground for efforts to more closely match the electrical results o... » read more

Why 450mm wafers?
By Chris Mack - 08 Aug, 2012 - Comments: 1

Why is 450-mm development so important to Intel (and Samsung and TSMC)? A few years ago, Intel and TSMC began heavily promoting the need for a transition from the current standard silicon wafer size, 300 mm, to the new 450-mm wafers.  While many have worked on 450-mm standards and technology for years, it is only recently that the larger wafer has received enough attention and support (not ... » read more

Firms Rethink Fabless-Foundry Model
By Ed Sperling - 31 Jul, 2012 - Comments: 0

By Mark LaPedus As chipmakers move toward 20nm designs, finFETs and 3D stacked devices, the industry is beginning to re-think the fabless-foundry model. Leading-edge foundries are finally getting serious about the “virtual IDM” model, in which vendors will act more like integrated device manufacturers (IDMs), as opposed to being mere production partners. In this model, the found... » read more

The Changing Role Of The OSAT
By Ed Sperling - 31 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler As process geometries and packaging technologies have matured over time, the OSAT (outsourced semiconductor assembly and test) provider has played an evolving role in the semiconductor packaging ecosystem. With true 3D chip stacking on the horizon, their role may evolve once again as ecosystem players jostle for position in the 3D universe. There are two things tha... » read more

Experts At The Table: Pain Points
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: Where will the pain points be going forward? Kariat: 20nm is... » read more

CNSE Readying NFX Fab for G450C, EUV Efforts
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By David Lammers Two key areas of the semiconductor industry’s future—the 450mm wafer transition and EUV lithography—are the focus of the new NFX (NanoFab Xtension) building now under construction at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. [caption id="attachment_6322" align="alignright" width="120" caption="Alain Kaloyeros"][/caption] T... » read more

Foundries Going Greener
By Ed Sperling - 26 Jun, 2012 - Comments: 0

The ongoing push towards green and energy-efficient systems is prompting the silicon foundries to jump on the bandwagon and devise their next-generation processes based on ultra-high voltage technology. For some time, several foundries have offered 1- and 0.5-micron, ultra-high voltage processes with ratings up to 800 volts. But seeking to get a jump for the next wave of designs, the special... » read more

Fabless-Foundry Model Under Stress
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Mark LaPedus The semiconductor roadmap was once a smooth and straightforward path, but chipmakers face a bumpy and challenging ride as they migrate to the 20nm node and beyond. Among the challenges seen on the horizon are the advent of 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the questionable availability of extreme ultraviolet (EUV) lithography. ... » read more

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