The Power Of Virtual Prototyping


As embedded SoCs continue to become more powerful and complex, beating the market may very well rely on non-traditional approaches to product design and development. Software-based methodologies involving virtual prototypes are helping to prove out designs earlier and enable companies to parallelize hardware and software development. Click here to download PDF. » read more

Accelerate SSD Software Development And System Validation


The amount of data coming at us or that we produce ourselves in our daily lives continues to grow exponentially. It’s become the norm to stream movies and TV series from Netflix, as well as upload our own videos on YouTube. On top of this, a major shift in automotive (ADAS, autonomous driving) and surveillance are boosting the amount of data exchange that is happening every second. With th... » read more

Partitioning Becomes More Difficult


The divide-and-conquer approach that has been the backbone of verification for decades is becoming more difficult at advanced nodes. There are more interactions from different blocks and features, more power domains, more physical effects to track, and far more complex design rules to follow. This helps explain why the number of tools required on each design—simulation, prototyping, em... » read more

Bulletproofing Virtual Prototypes


The big benefits of virtual prototyping methods are that they don’t rely on the availability of RTL or physical hardware. Instead they utilize modes of the future SoC. These models are typically lightweight and optimized for their use case, which is important in regards of simulation speed, modeling and testing effort. Model quality is a key concern, as the virtual prototyping end user accept... » read more

Which Verification Engine?


Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

Are You Designing The Right Product?


Development and production of SoCs is becoming more and more complex and expensive. And rightfully so, the semiconductor industry spends billions of dollars on verification efforts. Verification is about checking the design behaves per its specification, a process that is very important and well understood. Still, something can go terribly wrong because having a verified SoC does not guarant... » read more

Come Together Right Now Over… Virtual Prototypes


As a frequent traveler and gadgets enthusiast I love the concept of all my devices being connected. However, more often than not I experience a divide which is sometimes caused by bad software and sometimes caused by missing hardware interfaces. My recent frustration was related to my tablet missing a USB port to upload new maps to my GPS device. The GPS device became a divided, isolated pi... » read more

Hybrid Emulation


Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for [getentity id="22032" e_name="Cadence"]; Russ Klein, program director for pre-silicon debug products at [getentity id="22017" e_name="Mentor, a Siemens Business"]; [getperson id="11027" comment="Phil Moorby"],... » read more

Whatever Happened to High-Level Synthesis?


A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology that was to be the heart of a new [getkc id="48" kc_name="Electronic System Level"] (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high lev... » read more

Closing The Loop On Power Optimization


[getkc id="108" kc_name="Power"] has become a significant limiter for the capabilities of a chip at finer geometries, and making sure that performance is maximized for a given amount of power is becoming a critical design issue. But that is easier said than done, and the tools and methodologies to overcome the limitations of power are still in the early definition stages. The problem spans a... » read more

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