Thinner Channels With 2D Semiconductors

Moving to future nodes will require more than just smaller features. At 3/2nm and beyond, new materials are likely to be added, but which ones and exactly when will depend upon an explosion of material science research underway at universities and companies around the globe.

With field-effect transistors, a voltage applied to the gate creates an electric field in the channel, bending the band structure of the semiconductor to facilitate or impede current flow. In MOSFETs, specifically, the gate electrode serves as one plate of a capacitor and the channel as the other.

The gate capacitance, which depends on the dimensions of the gate and the properties of the gate dielectric, must be large enough to control the entire channel. Maintaining adequate gate capacitance is just one of many challenges as devices shrink, and they are motivating many changes to transistor design, as well as research into alternative channel materials.

As the channel length goes down, the channel thickness needs to shrink, as well. If the channel is too thick, the available gate capacitance may not be large enough, leading to short channel effects and poor channel control. FinFETs address the problem by wrapping the gate up and over one or more vertical fins. As the channel length continues to shrink, though, still more aggressive solutions are needed. Nanowires, nanosheets, and other gate all-around (GAA) transistor designs achieve better channel control by applying electric fields from all directions.

Making sufficiently thin gates in silicon is challenging. Below about 3nm, traps at the interface between silicon and the gate dielectric degrade carrier mobility. Two-dimensional semiconductors like WS₂ are being considered as alternatives because each monolayer has clean, self-passivating interfaces with no dangling bonds.

Electrostatic control of the gate is not the only factor device designers need to consider. As channel thickness goes down, so does the amount of current it can carry. Stacked nanowire and nanosheet designs use two or more channel layers to increase the total drive current.

Unfortunately, each additional layer adds leakage current, Xiaohe Huang, a researcher at Fudan University in Shanghai, pointed out at the December 2020 IEEE Electron Device Meeting. Depending on the device requirements, the balance between increasing drive current and limiting leakage current will define the number of layers that can be used. As in conventional transistors, placing a high dielectric constant material between stacked nanosheets helps control leakage by giving the same capacitance with a larger physical thickness.

For the best electrostatic behavior, the gates in a GAA structure should match each other as closely as possible, with the same equivalent oxide thickness and capacitance on all sides of the channel. At the same time, having an independently controlled back gate gives designers options that aren’t available with a single gate. In silicon-on-insulator (SOI) devices, the wafer itself serves as a back gate and can be used to tune the threshold voltage. Some 2D semiconductors, like WS₂, can take this idea a step further. In work presented at IEDM, Inge Asselberghs and colleagues at Imec reported that WS₂ devices are ambipolar, switching between hole conduction and electron conduction depending on the ambient field. They used a back gate bias to switch between hole and electron injection and define the polarity of the transistor, while the top gate switched the device on and off.

Still, realizing commercially viable transistors based on 2D semiconductors remains challenging. Imec’s test vehicles for manufacturing integration cannot yet match the performance of lab-grown devices, and simulated devices still outperform both. It’s difficult to say where the inadequacies of current fabrication techniques end and the physical limitations of the material begin, but both material deposition and contact fabrication pose major stumbling blocks.

Can 2D materials scale up?
The most commonly proposed 2D semiconductors are transition metal dichalcogenides (TMDs), including MoS₂, WS₂, and WSe₂. At this time, the best available devices are fabricated on freestanding flakes exfoliated from bulk material. The current best process for depositing WS₂ uses MOCVD at temperatures above 750°C, well beyond what gate metal layers can tolerate. Ongoing device development and process integration studies use layer transfer techniques, but manufacturers certainly would appreciate more process-compatible methods for wafer-scale deposition of device quality 2D semiconductors. While atomic layer deposition can produce thin layers, it generally leaves behind carbon and other contaminants from the precursor gases. Instead, sputtering or evaporation of the metal is usually followed by sulfurization or selenization.

Fig. 1: (a) Structure of a hexagonal TMD monolayer, with M atoms in black and X atoms in yellow; (b) hexagonal TMD monolayer seen from above. Source: English Wikipedia/Creative Commons

Instead of a uniform monolayer film, though, researchers usually see multilayer islands. Planar rotations of the hexagonal TMD lattice are energetically equivalent. Each island may have a different twist angle relative to the substrate, and each individual layer might be twisted relative to the monolayer under it. As the film grows and islands merge, grain boundaries form at the resulting edges. Transistor properties vary with the underlying island’s thickness and orientation. The resistance between layers of a 2D material is high, while the twist angle between layers changes the overall periodicity of the material.

Quentin Smets and fellow researchers at Imec identified 60 devices that were located on bilayer MoS₂ islands. With optimized SEM conditions, they were able to determine whether the bilayer region was below the source, in the channel, and so on. Islands did not appear to affect threshold voltage, but — regardless of island position — monolayer devices had better subthreshold swing behavior. Simulations suggest that thicker islands have more charge traps, degrading channel electrostatics.

At this spring’s Materials Research Society meeting, Penn State researcher Joan Redwing reported that depositing the transition metal at high temperatures (above 700°C) to facilitate uniform coverage. A three-step process first used high metal pressure to drive nucleation, then annealed the film in the chalcogen to promote uniform grain size, then used low metal pressure to encourage lateral growth without further nucleation. In WSe₂, higher temperatures increased the effective amount of tungsten and favored the formation of islands with tungsten-terminated edges. Still, bilayers started to form once coverage reached 50%.

Selective growth with substrate templates
Because it’s difficult to fabricate MoS₂ nanowires and nanosheets, it’s hard to disentangle the intrinsic properties of the material from the impact of defects. Instead of attempting to grow large area monolayers and pattern them, several results at the MRS Spring Meeting discussed selective growth of 1D nanowires/nanoribbons. Areej Aljarb, of Saudi Arabia’s King Abdullah University, observed that Ga₂ O₃ makes atomically sharp steps, which can provide a nucleation and growth shelf for MoS₂. Alternatively, work by Louis Maduro and colleagues at Delft University of Technology sulfurized Mo nanowires to create an MoS2 shell around the molybdenum wire.

Additional research, discussed by Yuzhou Zhao, of the University of Wisconsin – Madison, seeks to form Moire-patterned heterostructures from the bottom up instead of by stacking layers. This group used deformed SiO₂ spheres to distort the relationship between the substrate and the growing WS₂ film. They’ve demonstrated the ability to grow twisted multilayers, but haven’t learned to control the results yet.

Finally, broadening the catalog of 2D semiconductors beyond TMDs would give designers access to a range of band gaps addressing a variety of potential applications. For example, when graphene is made by etching SiC, a buffer layer forms between the graphene and the SiC. Intercalating boron or gallium into this region produces a monolayer encapsulated in graphene. Etching the graphene away with ammonia nitridates the intercalated metal. Redwing’s group at Penn State made 2D boron nitride and quasi-2D gallium nitride this way. Diffusion of the intercalated metal under the graphene limits the maximum area that can be produced with this approach.

Contacts on the edge
Even when high quality channel material is available, the unreactive character of 2D semiconductor surfaces makes contact fabrication challenging, too. While silicon reacts with metal to form conductive silicides, attempts to contact 2D materials often result in an insulating contamination layer. The key parameter for contacts is the Schottky barrier height, defined as the difference between the semiconductor conduction band and the metal work function. While silicon devices use dopants to adjust the band height, most 2D semiconductors do not yet have suitable doping schemes.

Even evaluating contacts can be challenging given the generally inconsistent channel materials that are available. In work presented at IEDM, Terry Y.T. Hung and colleagues at TSMC used asymmetric contacts to work around the problem. They fabricated devices with one edge and one top contact, both using nickel, then measured transport properties under both forward and reverse bias conditions. This approach essentially compares the device against itself, with the same geometry, same channel, and same defects in both directions. Edge contacts appeared to unpin the Fermi level, giving rectifying Schottky barrier contacts.

Edge contacts are attractive for other reasons, too. They are essential for contacting nanosheets buried in a multilayer stack. They also allow contact area to scale down as the device does, reducing the contribution of contact resistance. These factors and others may make edge contacts the next significant innovation in device design.

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