Experts at the Table: Semiconductor Engineering sat down to discuss extreme ultraviolet (EUV) lithography and other next-generation fab technologies with Jerry Chen, head of global business development for manufacturing & industrials at Nvidia; David Fried, vice president of computational products at Lam Research; Mark Shirey, vice president of marketing and applications at KLA; and Aki Fujimura, CEO of D2S. What follows are excerpts of that conversation. To view part one of this discussion, click here. Part two is here.
SE: EUV lithography is in production at the 7nm and 5nm logic nodes. We’ve heard some chipmakers are moving from EUV single patterning to EUV double patterning at 5nm and beyond. From there, we’re expecting to see high-NA EUV, which is in R&D. What are you seeing from your vantage point here?
Fried: If EUV had been deployed on its originally-slated schedule several years earlier, it would have been used as a single patterning scaling replacement and as a stepwise progression from 193nm immersion lithography. Unfortunately, it took longer than expected to get EUV established. This created a continuing need for multiple patterning with 193nm immersion, which includes self-aligned double patterning and self-aligned quad patterning. I worked on some early double-patterning initiatives using a 90nm reticle about 20 years ago, when self-aligned double patterning wasn’t truly viable. At the time, these efforts used a little trick that we played in the lab. Due to EUV taking so long to come to fruition, we built a much more robust version of double-patterning and quad-patterning to fill the void left by the lack of commercial EUV capabilities. EUV is now finally available, but it has come at a time when it can’t just be used as a single-patterning replacement. In several applications, EUV will most likely be deployed as the litho replacement during the litho step in double patterning. EUV still provides a huge advantage, since it will eliminate significant process time and complexity. Usually, these types of lithography scaling changes come with material challenges. I lived through the 248nm to 193nm lithography transition, and it was a difficult transition because many of the materials weren’t fully ready for manufacturing criteria. The equipment at the time was ahead of the materials. With EUV, it’s a little bit different. The equipment took so long to arrive and due to the extremely short wavelength, EUV introduced several unique material challenges. In addition, any stepwise progression in the fab has ripple effects into every other aspect of the fab. However, I believe there are adequate levels of innovation in all semiconductor fabrication sectors to support the progression to EUV along with the next big stepwise progressions.
Shirey: There is a tremendous amount of work being done across these generations of EUV. Starting with EUV reticles, there are inspection strategies being developed and deployed from initial qualification in the mask house to reticle re-qualification in the fab. As we try to squeeze more out of the current EUV systems, there is continuous development with resists and increases in source power that drive inspection and metrology characterization projects. There is ongoing work to optimize litho and etch inspection steps for EUV defects like stochastic defects in development and high-volume manufacturing.
Fujimura: High-NA is a clever invention. But the mask infrastructure needs to be shared between 193i and EUV, including high-NA. So in order for high-NA to be viable and attain a higher-numerical aperture, high-NA EUV uses 8:1 ratio of mask sizes to wafer sizes in one dimension while retaining the traditional 4:1 ratio in the other dimension. While EUV masks are substantially different in being reflective masks, mask sizes are the same for both. High-NA allows you to preserve that by deciding to split what used to be a full reticle design into two reticles. Each feature on a mask now reflects twice as much EUV energy off the reticle, improving the ability to write smaller features more precisely and reliably. Of course, 8:1 in both dimensions would be even higher NA. But that would either reduce the throughput of wafer manufacturing by 4X instead of just 2X. Or, it requires an entirely new mask infrastructure that handles much bigger masks, while also continuing to support the traditional sizes. High-NA will bring about opportunities to improve software processing infrastructure like inverse lithography technology (ILT) for wafer lithography and mask process correction (MPC) for mask writing.
SE: What are some of the new and enabling fab technologies on the horizon?
Fried: Lam has been public with a dry resist solution, which enables height scaling for depth of focus, high absorption and collapse margin. And that is a massive innovation that goes alongside EUV. There’s going to be all sorts of new innovations that go with that.
Chen: I’d highlight two technologies that we’re looking forward to now and in the future, both as a consumer of these technologies, and also as a contributor. First of all, as a fabless company, we’re concerned about the lithography challenges facing our foundry partners at leading-edge process nodes. Secondly, process control is becoming increasingly difficult because detecting sub-nanoscale defects is incredibly challenging. In both cases, we’re seeing good results with computational and AI-driven approaches. For example, we’re seeing the adoption of computational lithography used in conjunction with AI to optimize photomasks for yield. We’re also seeing AI being adopted to augment perception for defect inspection and metrology.
Shirey: More chip complexity and semiconductor demand are driving a lot of innovations in inspection and metrology. Some of the key inflections are EUV, nanosheets, advanced memory and automotive electronics. There is innovation happening for EUV reticle pattern quality monitoring for the very tightest leading nodes. Nanosheet and advanced memory are driving the need for inspection and measurement of buried structures, and there are continued innovations with optical and e-beam techniques as well as new technologies like X-ray metrology. At the leading edge there is an insatiable demand for higher capture rates of small defects, so there is continued innovation in light sources, sensors, and algorithms to ensure that inspection and metrology tools detect and measure smaller issues. With increasing silicon content in automobiles, there is innovation to inspect and measure for higher coverage screening applications with analytics to flag potential latent defects that could appear in the lifetime of the chip.
Fujimura: There are difficulties in going down to even narrower and smaller features. EUV double patterning will certainly be required. But even beyond that, we want to scale even more so that we can build a 20,000 core Nvidia GPU, for example. In order to accomplish that, we need the maximum amount of resilience to manufacturing variation on wafers, and therefore also on masks. Making a very small contact hole resilient to manufacturing variation is a key. If you just want the average of these structures to look okay, that’s not so bad. But in wafer and mask manufacturing, you need all of them to look okay. You need the worst-case examples to look okay. And that’s a really hard thing to do, particularly for lithography at these tiny dimensions. Any help that you can give it is a good thing. One of the ideas that was originally introduced by Luminescent many years ago is curvilinear ILT or inverse lithography technology. This is where you take advantage of curvilinear shapes on the mask to be able to produce a wafer that is more resilient to manufacturing variation. Even though we’ve known that curvilinear ILT shapes on a mask would improve resilience to manufacturing variation on the wafer, we couldn’t do it. The mask infrastructure couldn’t produce curvilinear shapes.
SE: The industry has removed some of the barriers to enable ILT curvilinear masks, right?
Fujimura: The first barrier, which has been removed, is multi-beam mask writing. In multi-beam mask writing, masks are written with pixel doses instead of individual rectangles or triangles. Multi-beam mask writers write masks at the same speed regardless of the complexity of the shape. The traditional variable-shaped beam (VSB) writers took too long to write curvilinear ILT shapes. But with multi-beam writing, curvilinear masks take the same time as masks that contain only Manhattan geometries. The second thing that happened was the use of GPU acceleration for mask data preparation and also for ILT that outputs the desired mask shapes. All of this allows a pixel-based software algorithm running on a GPU that processes, manipulates, and corrects mask or wafer shapes to process curvilinear shapes efficiently. So multi-beam writing and GPUs together enabled curvilinear mask shapes, both by processing pixels of identical size laid out in a grid, rather than by processing arbitrary rectangles or triangles. In the eBeam Initiative survey, an overwhelming majority of the industry luminaries believe that by 2023, we will be seeing a large number of curvilinear mask shapes on production masks.
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