Experts at the table, part 2: The impact and cost of air gap; reducing RC delay with liner-less approaches and cobalt; where EUV will make a dent…maybe.
Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for GlobalFoundries’ advanced technology development integration unit; Paul Besser, senior technology director at Lam Research; David Fried, CTO at Coventor; Chih Chien Liu, deputy division director for UMC’s advanced technology development Module Division; and Anton deVilliers, director of patterning technology and senior member of the technical staff at Tokyo Electron. What follows are excerpts of that conversation. To view part one, click here.
SE: Will air gap affect the number of masks and photolithography steps?
Fried: If you have eight masks to make a single line and via, one more to make the air gap is a small increase. Maybe you pick three or four levels. Intel is showing two right now. The number is small compared to the entire back end.
Child: But if you offer it and it costs more, and people have to design to it, the overall cost goes up. You can’t just take your existing design and air gap it. You’ll get some benefit, but you certainly won’t see the full potential.
SE: The goal for the dielectric constant of low-k was 2.2. We’ve never quite achieved that. The industry has been stuck at 2.4 or 2.5. Is there any hope of improving on that?
Liu: For the current low-k material, we are adding porosity inside to lower the low-k value. It already is showing improvement.
Fried: You’re going to start with a base k. You’re going to degrade it with liners. But if you can push down the base k, there will be an advantage. With high-performance logic, we’ve seen that any way you can push down base k you derive a product benefit from that capacitance reduction. It was done from 3.8 to 3.0 to 2.5 to 2.4. Every time we were able to squeeze a little bit of dielectric advantage, we got a product-level benefit from it.
Child: The good old days where we could pattern with one mask are gone. Double Patterning, or even triple patterning is gone. We’re in a situation where everything is uni-directional, and the integration to do that is very complicated. If you want to not have massive parasitic capacitance, you have to figure out how to take away all of these dummy lines. That dominates everything. You can reduce your k value with air gaps to almost nothing, and it doesn’t make any difference because you have massive parasitic capacitance. We’re in a different regime now. We have to fix integration to the point where k 2.4 versus k 2.45 matters.
Besser: I’ve seen a couple publications recently that go along this route. One is a publication on air gaps, where going to air gaps dramatically affects your Blech length. Going to an air gap reduces it by half. Intel came in at very high levels where they didn’t have to worry about that. The second thing is whether there is a pull for air gap from customers. The answer is no.
Liu: Sometimes there is bulk deposition k value that enters into the equation. People don’t know whether bulk material will be damaged after integration, especially after dry etch and post-etch clean. The work of etch is to take this material away. If you have a damaged layer, it could increase your effective k value. It also will affect reliability.
Fried: I have a tough time believing that replacement low k can be fundamentally equivalent to a current low-k scheme from a mechanical stability perspective. Is there any information on replacement low k surviving a CPI (chip-package-interaction) type of testing?
SE: What happens as we start moving down one more node, from 7nm to 5nm? The numbers vary, because different foundries are using different terminology. But as we move from one node to the next, what changes on the back end?
Liu: If we can use cobalt for the vias, it would give us a lot of room to address RC delay. If you can use cobalt as the via material, you can increase the height. And if you can do that, then you can lower the fragility and decrease the capacitance.
Fried: There is reducing liner thickness or going liner-less. There is reducing the film material and reducing the resistance of the absolute material. The point of scaling is you can implement all of those things at one node and get an actual benefit, but if you have a big enough pile of those all they do is keep the resistance fixed as you scale. You just need a big enough pile of these things. Getting rid of the liner at the bottom of the via is the most impressive. Getting rid of the liner on the sides still works. You get your cross-section back by using PVD metallization. But it piles up in the bottom of the via, and that what really punishes via resistance. It’s not just cross-sectional area loss. It’s having to go through those liners to get to the metal below. That’s a huge scaling benefit because it would allow you to get equivalent path resistance at smaller dimensions.
SE: We’ve been looking at EUV since 45nm. If it does materialize in commercially viable form, does it change what’s going on in the back end?
Fried: It fundamentally affects mask counts and costs. The first place we’re going to see EUV is in the cuts. Right now we do mandrel cuts for vias. That’s eight masks. If we see EUV, it will be in the cuts, so that will wipe three layers out with one. And the next place you’ll see it is in the vias, where you can wipe out four layers with one. You can see significant litho pass reduction right away in the back end.
Child: EUV is not ready yet. It’s getting there. But the question we all need to ask is, ‘When is it going to be ready?’ Right now, we can do cuts and holes. We have processes that are capable. Can we do metal patterning directly? Not really. We’re not quite there yet. So you have this timeline for getting to this point, and the problem is when we get to the next node, is EUV ready? And if it is, do we still have to resort to multiple patterning with EUV. The assumption right now is that we get to the point where we can do one metal patterning and replace all of the metal patterning that we do now—the SADP, SAQP or whatever—with cuts. You take two or three masks out of the equation right away. But what if we’re at the point where the pitch has to go back to SADP. Then the cost benefit goes away. So we can see an EUV benefit, but it’s not clear if we can actually realize it.
Fried: There are two main areas of EUV cost savings. One is knocking out passes. That’s possible before EUV is ready. People are still developing design rules to knock out some passes, which is purely manufacturing cost savings when it can happen. But the real benefit is when you actually plan for EUV and you develop 2D design rules that leverage the patterning fidelity of EUV, so you win on a density perspective. That’s not just substituting litho passes and pattern schemes. You design tighter because you leverage that tighter fidelity.
BEOL Issues At 10nm And 7nm (Part 1)
Lines blur with middle of line as RC delay increases, reliability and yield become more difficult to achieve, and costs skyrocket.
Pain Points At 7nm
More rules, variation and data expected as IP and tools begin early qualification process.
Uncertainty Grows For 5nm, 3nm
Nanosheets and nanowire FETs under development, but costs are skyrocketing. New packaging options could provide an alternative.