Selective deposition is showing promise in the lab, but it’s a long way from there to production.
For years the academic community has explored a novel technology called selective deposition. Then, more than a year ago, Intel spearheaded an effort to bring the technology from the lab to the fab at 7nm or 5nm. Today, selective deposition is still in R&D, but it is gaining momentum in the industry.
With R&D funding from Intel and others, selective deposition, sometimes called ALD-enabled nano-patterning, is moving beyond academia. At a recent event, Intel, TEL and several universities presented papers on selective deposition. And behind the scenes, other foundries and fab tool vendors are also exploring the technology.
Intel, for one, believes selective deposition represents a new paradigm shift for patterning at future nodes. It’s a technique that patterns chips from the bottom up at the atomic level. The technology doesn’t replace today’s lithographic techniques, but it does reduce the number of patterning steps in the flow.
For decades, chipmakers have used deposition, a process that deposits a blanket of materials on a surface. In contrast, combining novel chemistries with Atomic Layer Deposition (ALD) or molecular layer deposition (MLD), selective deposition involves a process of depositing materials and films in exact places.
One of the applications for selective deposition is to address the problematic alignment issues for the critical layers in chips, namely the back-end-of-the-line (BEOL). With that application in mind, Intel says the technology could potentially solve one of the biggest roadblocks in chip scaling—edge placement error (EPE). EPE is measured as the difference between the intended and printed contours in a layout.
“This is really the key metric, and one of the most critical things, in lithography today,” said Florian Gstrein, who is in charge of the EUV Lithography and Novel Materials Research Group within the Components Research Lab at Intel. “Edge placement error is the biggest risk for Moore’s Law. It’s the biggest risk to scaling that we face.”
Moore’s Law, the observation that describes the pace of chip scaling, is slowing as the industry migrates towards 16nm/14nm and beyond. It’s not clear whether the current or futuristic IC-manufacturing techniques can get Moore’s Law back on track.
Intel has high hopes for selective deposition, but bringing the technology from the lab to the fab is no simple task. To be sure, the technology is still in its infancy. The processes are complex and defectivity remains a concern.
“When it comes to ALD-enabled nano-patterning, there are several obstacles to be solved for industrial applications,” said Han Jin Lim, a technical staff member at Samsung’s R&D Center. “Local roughness control of the lines or contact patterns by selective deposition is critical. A proper level of control for random defects is also important.”
Why selective deposition?
Chipmakers are looking at selective deposition and other futuristic technologies for good reason. Lithography, the key enabler for chip scaling, remains in flux and the industry is in need of new breakthroughs.
For example, today’s 193nm immersion lithography is expected to extend to 10nm. Then, at 7nm and beyond, there are still a number of options on the table. Extreme ultraviolet (EUV) lithography is the frontrunner at 7nm, but it’s unclear if EUV will be ready on time.
So amid the uncertainly with EUV, the industry must keep its options open and prepare for a number of scenarios. “You could see any of the known methods being used, such as multi-patterning, EUV, directed self-assembly, or direct-write,” said David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics. “EDA would primarily be affected by which patterning technique is used. The design rules and special checking or coloring requirements vary by process and the dimensions of the pattern being imaged.”
In any case, there’s another option in the mix, namely selective deposition. So where does this fit in?
For years, Intel has used a 1D layout scheme to simplify its IC design and manufacturing process. Other foundries are also moving from 2D to 1D layouts. To enable 1D layouts, Intel uses a two-step process to pattern a wafer—lines and cuts. For this, the first step is to make straight lines or gratings on the wafer using 193nm immersion lithography. Then, the lines are precision cut into exact patterns.
The line and cut patterns must be exact and aligned properly on each layer. If they aren’t aligned, it causes a misalignment and overlay errors. And overlay errors contribute to EPE, which will impact the performance and yield for a design.
Overlay and EPE are becoming more challenging at each node, prompting the industry to look for new solutions like selective deposition. In one simple example of selective deposition, a tiny metal strip is selectively deposited between two lines on the device. In effect, the metal strip acts as a guide between the lines, preventing a misalignment in the pattern.
This sounds simple, but it’s actually a daunting task. “There are a couple of places where selective deposition has been done in the past. But the applications have been pretty specific, where we have gotten our arms around the defectivity issues,” said Dave Hemker, senior vice president and chief technology officer at Lam Research. “But anytime you go selective and deposition, you’ve have to make sure the defectivity and other issues are solved. As we learn more about it, we’ll see more applications coming out of it.”
Meanwhile, selective deposition is related to today’s ALD. Used in today’s fabs, ALD tools deposit materials layer by layer. ALD involves a binary process with two reactants—A and B. The first reactant, A, is pumped into the ALD chamber. The wafer is processed and then the chemistries are purged. Then the second reactant, B, undergoes the same step.
Selective deposition also uses ALD, but it’s different than traditional ALD. “The difference is you somehow trick the ALD process, so that it grows on material A, but does not grow on material B,” said James Engstrom, a professor in the School of Chemical and Biomolecular Engineering at Cornell University.
In selective deposition, ALD is used to selectively deposit inorganic compounds. MLD and ALD are similar, but MLD deals with organic materials. Both ALD and MLD can be used to deposit metals on metals and dielectrics on dielectrics on a device.
The industry is making more progress in depositing metals on metals. “It’s more difficult for dielectrics than metals,” said Gregory Parsons, a professor in the College of Engineering at North Carolina State University. “The basic difference is in the reactivity.”
Still, the question is clear—Can it work in a fab? “This is one of the questions we are trying to get at in some of our modeling experiments,” Parsons said. “The question is how good can this be? People talk about having a 99.99% yield. That’s not going to cut it. At 99.99%, that’s nowhere near the kind of purity or defect control you need in order to get this transitioned from the lab to the fab.”
Lab to the fab?
To bring selective deposition into the fab, the industry will require three technologies—the right hardware, the proper chemistries, and a sound flow. On the hardware front, the industry uses third-party or custom ALD tools that are generally geared for R&D. “We are all looking for solutions in selective deposition,” said David Chu, strategic marketing director at Applied Materials. “The development of that is limited by the fact that the available toolsets are limited.”
What’s required is a new ALD technology, Chu said. Applied Materials, for one, is pushing spatial-based ALD for current and future applications. Unlike traditional single-wafer ALD, spatial ALD is performed in a mini-batch system. Wafers are placed in a system. The wafers travel to various zones and are then processed.
Finding the right chemistries is another challenge. “In order to make ALD-enabled nano-patterning available in the semiconductor industry, careful ALD precursor and reactant selections are required,” Samsung’s Lim said. “And a cost-driven seeding process should be developed.”
Chipmakers must also investigate the various process flows. According to Cornell’s Engstrom, there are three basic ways to deploy the technology—blocking layers; promoters; and inherent selectivity.
For some time, researchers have been exploring the blocking layer approach, sometimes called area-deactivation. For this, a tool deposits a self-assembled monolayer (SAM) chemistry on a surface. This forms a tiny mask on the surface. Then, the desired material is deposited on the surface. So, the material nucleates on the surface area not covered by the mask.
“With SAM, it might be possible to do selective-area ALD or CVD by area-deactivation,” said Erwin Kessels, a professor at the Eindhoven University of Technology. “But this only provides a solution in cases where the substrate is already patterned. Selective deposition by area-deactivation doesn’t really help you in most cases when you really want to generate patterns from the bottom-up, which is the ultimate aim. Yet, it would still be helpful to reduce the number of litho steps.”
Meanwhile, the promoter technique, sometimes called area-activation, is gaining steam. Generally, in this approach, a seed layer is deposited on select portions of the surface using ALD. The seed layer reacts to the surface. The desired material grows on the seed layer, but not on other portions of the surface.
Eindhoven University of Technology is working on one version of this approach—direct-write ALD. For this, the surface is patterned using a novel electron-beam induced deposition (EBID) tool. “In our recent work, we have spent a lot of time on the demonstration of the method to fabricate real devices for channel materials, such as carbon nanotubes or graphene,” Kessels said. “The carbon nanotube devices work very well with high on-off ratios. The graphene devices show high field-effect mobilities and low contact resistance, demonstrating that the bottom-up method is well suited to make nano-contacts with graphene.”
Meanwhile, in its latest work, North Carolina State developed a mechanism for metal thin-film formation by surface reduction. “In this case, we used tin as an example metal,” North Carolina’s Parsons said. “We believe that this surface reduction process could lead to some inherent selectivity in metal nucleation. One example application for tin is nanowire FETs. We are exploring ALD of tin into nanoporous solids as a means to produce the desired structures, although we have not reported any of those results yet.”
And not to be outdone, Cornell is developing a slightly different version of this approach. “It is not really inherent selectivity, but perhaps induced inherent selectivity,” Cornell’s Engstrom said. “All metal-containing precursors used in ALD are compounds. (They can be) inorganic or organometallic. For growth to occur, the precursor must chemisorb dissociatively, forming some molecular fragments. If you can get the metal-containing chemisorbed fragment to recombine with another species to form a species that desorbs, you can obtain reverse adsorption.
“The trick comes in what precursor to choose, and what adsorption reversal agent to add to the process,” he said. “This idea is quite generic, and could work with many ALD chemistries. The possible chemistries are as diverse as ALD itself.”