The ability to shrink devices will continue for at least four more nodes as EUV begins to ramp, but it’s just one of a growing number of options.
Moore’s Law has been synonymous with “smaller, faster, cheaper” for the past 52 years, but increasingly it is viewed as just one of a number of options—some competing, some complementary—as the chip industry begins zeroing in on specific market needs.
This does not make Moore’s Law any less relevant. The number of companies racing from 16/14nm to 7nm is higher than the initial rush to finFETs at 16/14nm, according to numerous industry sources. But that migration also needs to be put in perspective:
• Node naming became meaningless after 20nm, when foundries leveraged the same back-end of line measurements using 16/14nm finFETs. Consequently, there is no agreed upon definition for what is 10nm or 7nm. A more useful number is a comparison of performance and power by individual foundries.
• Even the strongest proponents of Moore’s Law are slowing from one node ever two years to a node every three or four years. But industry sources say a number of companies plan to skip nodes due to rising cost and complexity, so rather than turn out a production chip at every node, they plan to develop test chips to stay current on the latest technology, while delaying their move of production chips for as long as eight years.
• Big systems companies, such as Apple and Google, are developing chips that defy standard measurements because they are application-specific and heterogeneous. In comparison, most node-specific measurements are based on ASICs, not ASSPs. Moreover, those statistics are generally not included in semiconductor industry statistics because the systems companies don’t share them.
As a result, how much of the semiconductor industry is truly following Moore’s Law is no longer a straightforward exercise in counting. Logic devices are still shrinking, but not at consistent or comparable rates. And as advanced packaging begins making more inroads, what goes into those packages could be a combination of anything, including logic chips made at the latest process geometry coupled with IP developed at older nodes.
“For the past 50 years, the cheapest and easiest way to increase complexity was to shrink the feature size and grow the wafer diameter,” said Wally Rhines, chairman and CEO of Mentor, a Siemens Business. “It’s not the easiest way anymore. There is a tradeoff. We will do the things that are most economic for the capabilities we want. Some of those will keep us going with smaller and smaller feature sizes almost forever. But the most economical tradeoff is likely to be a combination of better system engineering, multi-chip packaging, and a whole variety of other techniques to keep advancing the capabilities in the most cost-effective way.”
The changes, collectively, represent a different way of looking at the benchmarks for progress in semiconductor design and manufacturing. “Fundamentally, Moore’s Law is about every year delivering more performance and scaling power,” said Simon Segars, CEO of ARM. “There are many dimensions to that other than just making the transistors and gates smaller to the point where we run into the fundamental size of an atom and that’s it. For many generations, it was just about scaling. And then people started thinking, ‘What if we use some different materials here and materials science.’ That has made enormous improvements. We’re only just about to see EUV being introduced. That’s going to breathe new life into scaling transistors and technology. And meanwhile, people are looking at other ways to do computing, such as quantum computing. That relies on a totally different set of technologies. Yet once delivered—and it may take 10 years—that will deliver vast new degrees of parallelism that will look like another few generations of Moore’s Law.”
Ever since double patterning became a requirement on the critical metal layers—namely metal 1 and metal 2 at 20nm—most experts assumed that the primary limiting factor for device shrinking would be lithography.
Fortunately, though, chipmakers have been able to extend traditional optical lithography. Using various multiple patterning schemes, chipmakers are able to split the mask and pattern each one separately. In doing so, they can extend today’s 193nm wavelength lithography to 16nm/14nm, 10nm, and even 7nm.
But at 7nm or 5nm, the pattern complexity and mask counts are becoming limiting factors for immersion/multi-patterning. A 28nm device has 40 to 50 mask layers. In comparison, a 14nm/10nm device has 60 layers, with 7nm expected to jump to 80 to 85. At 5nm, there could be 100 layers.
To simplify the flow at 7nm and/or 5nm, chipmakers have been waiting for extreme ultraviolet (EUV) lithography, a 13.5nm wavelength technology. EUV was expected at 45nm, but ran into a number of issues that only recently have been resolved. As the power source increases, and throughput continues to rise, it appears that EUV is finally close to being used for commercial production.
Whether close is good enough for mass production remains to be seen. “We have 100 wafers per hour in the factory,” said Hans Meiling, vice president of service and product marketing for EUV at ASML. “We’ll upgrade that later this year to 125 wafers per hour.”
Uptime, meanwhile, has increased to more than 80% based on 11 four-week averages. Meiling said the goal is 90%-plus, which is comparable to immersion lithography. The fact that it has reached this point, though, is nothing short of astounding. This project looks like something straight off the pages of a science-fiction novel.
There are a number of engineering tricks in here. The first is to get a steady stream of tin droplets from a small droplet mechanism. Those droplets are hit with a laser. Then, the laser unit fires again, which is the main pulse. The main laser pulse hits the pancake-like tin droplet and vaporizes it, which, in turn, becomes plasma. The plasma emits EUV light at 13.5nm wavelengths.
“There are 50,000 droplets per second,” Meiling said. “It’s a controlled process. They go in a high velocity stream at hundreds of meters per second. And then we have a CO² laser that hits every droplet. So the rate of the CO² laser is the same as the droplet generator. Every droplet gets turned into a pancake. Because of the CO², it expands to 200- to 400-micron mist, instead of a solid. The first pulse makes it a pancake.”
Even more astounding, it works. There is a growing body of documentation to prove that.
But in spite of these improvements in lithography, the limits of scaling are becoming more apparent in many places. Layout flexibility decreases at each new node. Intel was able to move to 1D patterning at 45nm largely because a CPU doesn’t need the same level of flexibility as an SoC. Its structures are much more regular. For an SoC or ASSP, that is much more limiting.
“Our take on this is that with EUV, two-dimensional patterning will be too difficult,” said Yang Pan, CTO at Lam Research. “First, EUV still has mask defect issues. You have to repair these defects, but you can’t keep doing repair after repair. And second, if you want to get good line-edge roughness performance for EUV, you need a lot of power. That is not possible today. So EUV will go to a one-dimensional line and space. We don’t see 2D at this point.”
There are other limitations, too. “The main thing is that EUV addresses the resolution,” said Raman Achutharaman, vice president and general manager of Applied Materials‘ Etch Business Unit. “It doesn’t address the overlay requirements. The second part is that the longer EUV gets pushed out, you will need multi-patterning even with EUV. For cuts and vias, EUV can be used. But lines and spacers, you use a spacer-based approach.”
Still, there has been progress, thanks in part to a massive investment by multiple companies and a recognition that EUV is much closer to becoming production-worthy. Until last year pellicles were a problem, as well. No one wanted to take responsibility for developing pellicles, so ASML developed its own. And it will take time before EUV moves into production for lines and spaces rather than just mask cuts. But the pieces are now sufficiently developed that from here on the technology will gain some momentum.
How quickly that happens is a function of many other factors. But from a pure lithography standpoint, ASML says that EUV now has a clear path all the way to 1.5nm—and possibly beyond, with the help of higher numerical aperture technology and an anamorphic lens, which can extend the laser across a larger surface like an old CinemaScope projector used for showing widescreen movies.
“On the chip side, the challenges are basically to fight the line edge roughness and the photon shot noise that is there,” said Jan van Schoot, senior principal architect at ASML. “We have to focus so that we get enough power on the wafer. You can fight photon shot noise basically in two ways. You can apply the brute force method, applying more photons and you have better statistics. You also can try to improve the contrast of the image that you’re applying to the wafer. That is the more elegant approach.”
Other back-end changes
EUV significantly reduces the number of mask layers required to create chips, which speeds time to silicon. Industry sources say it now takes about 60 to 90 days to get silicon back from foundries for advanced chips, which is up from about 45 to 60 days at previous nodes. Reducing the number of masks using EUV has a direct bearing on that.
But mask reduction is only one factor. Process variation continues to be a major problem, as evidenced by the growing body of design rules. “Design rules are increasing, and the number of operations needed to complete design rules is increasing exponentially,” said Christen Decoin, director of product management at Cadence. “DRC cannot be run overnight anymore. Altogether, it takes four days. With EUV, there are less coloring rules. But it arrived so late that we still need double patterning, although complexity will not be as bad at 7nm.”
Process variation increases at every new node. Specifications are never printed at the exact number, so one mask has a different variation than another. While this is typically dealt with in design tools, the approach is to increase timing margins. The tradeoff is lower yield or higher performance. This is one of the less-advertised selling points of FD-SOI, in part because the foundries offering FD-SOI have to dance a fine line with their advanced node technology.
FD-SOI is just one of a number of options, though. Scaling is becoming more difficult, for sure, but it also is becoming more expensive. As a result, some chipmakers are looking at a number of alternatives to scaling that can extend their technology investments. So rather than moving to 10nm, some have jumped to 7nm. And at 7nm, they could move to 5nm, or stay at 7nm with a different architecture.
“There are still a lot of things you can do with the architecture of a device,” said Ivo Raaijmakers, CTO of ASM International. “You can change the gate length with nanowires at 5nm. But fabs are getting more expensive and R&D is getting more expensive, and there are an increasing number of other technologies available.”
Raaijmakers said the tradeoff is doing one step at existing nodes, or multiple steps at future nodes, or making the next node sufficient for multiple iterations of chips. “The big challenge with density is controlling parasitics like capacitance and resistance.”
Packaging: Moore’s Law in pieces
That hasn’t gone unnoticed, which is why there is so much activity these days on the packaging front. Advanced packaging adds an entirely new way of looking at Moore’s Law. Rather than requiring memory, processors and I/O to be developed at the same process node, it allows the blending of pieces developed at different nodes.
This opens up new degrees of freedom for chipmakers. In the past, the big worry was how much would fit onto a piece of silicon. That caused a long list of issues, primarily involving throughput and heat. Resistance and capacitance affect the speed at which signals travel through increasingly thin wires. That resistance also generates heat, which can cause signal integrity issues, electromigration, and it can cause quality degradation over time. On top of that, there is routing congestion and contention for on-chip resources. And below 45nm, analog IP no longer shrinks, which is why analog IP makers have added more digital circuitry into their products.
Fan-outs, system-in-package, and 2.5D configurations radically alter this equation. Flows are still being developed to simplify this process, but there has been a rapid uptick in interest in this approach over the past couple of years, and particularly in the past 12 months with Apple’s adoption of TSMC’s Integrated Fan-Out (InFO) for its iPhone 7 processor, and high-end networking 2.5D chips from companies like Cisco and Huawei.
TSMC’s InFO uses fan-out wafer-level packaging, which sits roughly between 2.5D and organic substrate system-in-package in terms of lines and spaces. All of those can utilize the most advanced process nodes for logic, combined with other chips or IP developed at older nodes.
The key here is how the chips are put together to make electrical connection. Seung Wook (S.W.) Yoon, director of product technology marketing at STATS ChipPAC, said one new approach is to use interlayer dielectrics rather than bumps to connect the die. “This is more reliable than a flip chip, and it still has no bumps or pads.”
There are many more packaging approaches in the works, as well, and for IP vendors this is a huge benefit because they can still sell technology developed at older nodes for the most advanced chips. In the case of analog IP, that’s a huge savings in time and development costs for IP vendors. But it also provides more options for chipmakers to reduce costs because they don’t have to shrink everything down onto the same die. That has spawned much more cooperation and interest across the semiconductor industry.
“This is no longer lunatic fringe stuff,” said Mike Gianfagna, vice president of marketing at eSilicon. “We just finished a 2.5D design a few weeks ago using HBM (high-bandwidth memory) and a large ASIC, which will be in production later this year. This isn’t just ASSP vendors anymore, where they have a totally captive market and cost is no object. This is moving to ASICs, which means the whole ecosystem is working on this—the customer, the ASIC vendor, the wafer vendors, the IP vendors. It takes teamwork to make design happen. A few years ago, there is no way that would have worked. It was a secretive community. Now everyone is talking.”
Tying this all back into Moore’s Law may or may not make sense. The original observation was fairly straightforward, but it has been reinterpreted so many times that it’s hard to say what is or isn’t Moore’s Law anymore. As Synopsys Chairman and Co-CEO Aart de Geus put it, “If you say Moore’s Law is strictly economic, it is under pressure. But from a technological point of view, there are still a lot of places to go. Eight years ago the argument was that finFETs were not going to happen because they were vertical, extremely fragile constructs that economically made no sense…The only rule of Moore’s Law is never say never.”
Coming in part two: Front-end issues, economic shifts, and the impact of Moore’s Law on von Neumann architectures.
Why EUV Is So Difficult
One of the most complex technologies ever developed is getting closer to rollout. Here’s why it took so long, and why it still isn’t a sure thing.
Next EUV Challenge: Pellicles
Protecting photomasks at high temperatures is proving difficult and expensive.
Betting On Wafer-Level Fan-Outs
Chipmakers focus on packaging to reduce routing issues at 10nm, 7nm. Tool and methodology gaps remain.