Pathfinding Beyond FinFETs

What structures and materials will be needed at 5nm and beyond.


Though the industry will likely continue to find ways to extend CMOS finFET technology further than we thought possible, at some point in the not-so-distant future, making faster, lower power ICs will require more disruptive changes. For something that could be only five to seven years out, there’s a daunting range of contending technologies. Improvements through the process will help, from EUV lithography and six-track design, to new materials like cobalt and ruthenium for interconnects and SiGe for channels, but new device structures will be needed before long, with researchers eyeing a smorgasbord that includes nanowires, carbon nanotubes, tunneling, monolithic 3D, spin and 2D materials.

imec image, Pathfinding
Top line is historical scaling improvement. Dashed lines are actual and projected results from scaling alone since ~2012. Blue line is potential results achievable by combined improvements in lithography, materials, device type, design, and systems-level optimization. Source: imec

Gate-all-around nanowires could outperform finFETs at 7nm
As finFETs’ potential gains in speed and power start to slow at 7nm, simulations suggest gate-all-round nanowires start to look like a better option, contends An Steegen, imec senior VP of Process Technology, who will discuss these issues in the “Pathfinding Beyond 5nm” program at SEMICON West 2016 on July 12. While finFETs allowed both >40% voltage scaling (dynamic power in µW) and >20% performance gains (GHz) in moving from 14nm to 10nm, gains from moving to 7nm FinFETs will be only <30% and <15%, respectively, whereas a 7nm nanowire device should see greater >44% improvement in power and >20% improvement in performance, and similar scale gains at 5nm as well.

Imec makes the nanowires by epitaxial growth and etch of fins of alternating layers of Si and SiGe, selectively etching away the SiGE to leave a nanowire of silicon, then deposits the dielectric and metal layers around it. imec also has demonstrated

In 7 to 10 years, imec researchers see the need for III-V and 2D materials, new switching mechanisms such as tunneling or spin, and optimization at the system level by various types of 3D integration, as key to continued improvements in performance.

CNTs demonstrate
Carbon nanotubes (CNTs) could potentially solve a major part of the scaling problem by their intrinsic 1nm diameter size, with IBM researchers have made progress on the key issue of making low-resistance contacts at very small scale by making atomic-level metal-to-carbon bonds at the zero-dimension point contact at the end of the CNT. The dimensions of the deposited metal along the tube are limited by lithography, but they don’t much matter, as the bonding and actual current injection only occur at the open CNT end point contact area where the tube has the necessary available sites for bonding. While the published research required higher temperatures than practical for manufacturing, more recent developments have reduced this sharply enough to be interesting, says Han.

CNTs also have the advantage that they can be used for both p-FETs and n-FETs, by using contact metals with different work functions. High density, evenly pitched CNT alignment remains a key challenge, though. While a number of research groups grow nicely aligned CNTs on one substrate and then transfer them to the device substrate and remove the metallic CNTs from the as-grown mix, a more practical approach for uniform volume manufacturing will require depositing and patterning an already-purified, all-semiconducting CNT solution directly on the device wafer. This typically involves making a template on the substrate with conventional lithography and etch, and then functionalizing one part of that pattern to attract the CNTs from solution. “We target 10nm spacing, and we’re now at about 5X that,” Han notes.

TFETs outperform CMOS at low voltage
The tendency for electrons to tunnel through a barrier at small dimensions offers a promising lower-voltage switching mechanism for scaling beyond finFETs, as it becomes harder to reduce the energy per operation of CMOS much further without reducing performance. Tunnel FETs outperform CMOS at low voltage, but getting enough on-current through the tunnel barrier to be practical remains a challenge.

Some of the best recent results come from the labs of Suman Datta, who will give an update at SEMICON West, July 12-14 in San Francisco. He and colleagues at the University of Notre Dame and Pennsylvania State have demonstrated a III-V heterojunction tunnel FET with both low operating voltage and record high on-current (though not yet at target levels to beat CMOS). One key has been progress in cleaning technology to achieve a high-quality interface with a low density traps between the highly reactive InGaAs (nFET) and GaAsSb (pFET) channels and the dielectric. “You have to clean the material within the chamber internally so it doesn’t grow a native oxide,” says Datta. “We’ll need more comprehensive cluster processing with insitu clean for these stacks.”

One option for reducing the operating voltage of future logic circuits is complementary p-type and n-type heterojunction tunnel FETs formed with a common metamorphic buffer technology. Source: Suman Datta, Penn State and Notre Dame. Compound Semiconductor Magazine.

Manufacturing TFETs also will require advances in epitaxy to build the complex III-V nanocolumns, and figuring out how to etch the stacks of materials that all etch at different rates. “But many of these TFET scaling issues are the same as those for MOSFETs, so depending on the where the insertion point is for TFETs, many of these issues of integrating alternate channel materials on silicon may be already solved,” Datta notes.

“What comes after finFETs is hard to predict, but at 5nm technology node and below finFETs are likely to see a drop in performance due to short channel effects,” he notes. “Gate-all-around nanowires seem a more familiar technology, but they do start with a fin. And while finFETs get great drive current per footprint, once you break that up into several nanowires, you lose that drive current advantage. You’d probably need to break the fin into four nanowires to get enough current, so why not just make a taller fin and find other means such as junction design to control short channel effects?”

These speakers will be joined by others from CEA-Leti on monolithic 3D integration and Synopsys on performance simulations in the “Pathfinding Beyond 5nm” program at SEMICON West 2016 on July 12. Other related sessions focus on nearer term scaling issues, next-generation interconnect, and university research programs.

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