Advanced packaging challenges grow as chips and package sizes shrink; different equipment, technologies gain traction.
Bumps are a key component in many advanced packages, but at nanoscale levels making sure all those bumps have a consistent height is an increasing challenge.
Without co-planarity, surfaces may not properly adhere. That can reduce yield if the problem is not identified in packaging, or it can cause reliability problems in the field. Identifying those issues requires a variety of process steps, including various types of inspection and metrology. The denser and smaller the bumps, the more intensive and time-consuming those processes become.
“As I/O pitch within the die continues to decrease, the number of needed bumps per die increases. Also, the bump size is continuing to decrease,” said Doug Scott, vice president of wafer services at Amkor. “In some cases, there may be over 5,000 bumps per die. This requires each bump to be the same size and shape to ensure proper assembly downstream. One missing bump or a malformed bump will lead to assembly failure and yield loss.”
There are other challenges, as well, particularly as die included in those packages become more heterogeneous. “The total power delivered into new nodes is generally still going up, which is pushing customers to die with mixed bump pitches and bump diameters,” said Mike Kelly, vice president of advanced packaging development and integration at Amkor. “This requires higher-end plating tools and generally slower plating times, and there is a drive to minimize cost impact. Our customers’ biggest concern is total current, which is primarily an electromigration concern, but it is also a finer grid delivery of current into new silicon nodes — especially with 3nm, but starting also with 5nm. This means more bumps on finer pitch and potentially more plating challenges when bump pitches and bump diameters vary across the die.”
Construction
Bumps are simply spheres of solder, generally ranging from 75μm to 200μm in diameter. They can be formed using electroplating or direct placement. “Both processes are well understood, well optimized, and successful in high volume manufacturing,” said Scott. “Solder bumps can also be made using screen printing, but there are yield/solder voiding concerns. Proper design between the bumped die and substrate/end PCB can significantly reduce failure points.”
Bumps are implanted on ICs in the flip-chip process — technically, controlled collapse chip connection, or C4. Once a die is fabricated on a wafer, a metallized pad is placed on top of it and the bumps are attached. Then, the chips are diced and flipped over.
Fig. 1: Parameters that must be controlled for bumping processes include height, coplanarity, position, size, and shape. Source: CyberOptics
Ideally, the bumps are then perfectly aligned to connectors on other components. This is where problems often occur, either due to defects in the bumps themselves, or substrate warpage which prevents the bumps from properly lining up.
“Interconnections between chiplets rely on microbumps with a solder thickness of less than 10 microns,” said Marc Swinnen, director of product marketing for Ansys‘ Semiconductor Division. “The solder volume of a microbump is approximately two orders of magnitude smaller than a traditional flip-chip joint. This means that even slight bending or warping of the interposer substrate poses significant reliability risks. In addition, these microbumps are being called on to collectively carry hundreds of watts of power. Any local overheating can lead to thermal failure of these tiny structures.”
“You have a wide range of materials, different substrates, and all of them have different coefficients of thermal expansion,” said Frank Chen, director, Applications and Product Management at Bruker Nano Surfaces & Metrology. “Whenever you have these mismatches, some things will cool faster than others and you can get a lot of warpage and stress that you can’t eliminate completely. The reality is it’s very hard to get a flat surface.”
In many cases, this warpage is so small that it requires special equipment to even detect it.
“What’s really challenging people are the three main types of bump defects — bridges, non-wets, and voids,” said Chen. “But there’s also metrology types of problems, such as die placement errors, which include die-shift and rotation. Another problem associated with die-attach is the pressure. The typical process is to apply pressure and heat to attach the die, but you could have some tilt or warpage because the pressure or heat distribution wasn’t uniform.”
Voids, which can make a solder attachment interface look like Swiss cheese, are a source of thermal and power problems. “Voids are known to be very poor thermal conductors and interfere with the heat transfer away from the component,” said Anders Schmidt, application engineer at Palomar Technologies. “Because the component cannot dissipate heat well, its current carrying capacity decreases, leading to inefficient power utilization.”
Fig. 2: Swiss-cheese like voids can cause many problems, including poor thermal conductivity. Source: Palomar Technologies
Worst case, voids can lead to cracking in the die. The solution, according to Palomar, is to use eutectic bonding, in which the melting point is lower than the melting points of each individual material. This can be accomplished using an intermediate metal layer. “Having a very low melting point during bonding, but not during the operation of the device, is one of the key attributes of eutectic bonding,” Schmidt said.
Because solder bumps are metal, they also can help with thermal dissipation. “A reliable solder bond will work in conjunction with the package to dissipate internally generated heat, maintain long-term functionality when subjected to operating temperatures, and withstand shock due to environmental conditions or power cycling.”
Evolving Materials
First introduced by IBM in 1964 [1], the bump design became popular as components shrank because they enable more I/O connections in the same amount of space as wirebonding, while also lowering thermal resistance and inductance.
Originally, bumps were made from tin-lead (SnPb) alloys. In keeping with current environmental concerns, they are now more often made from a tin-silver-copper (SnAgCu or SAC) alloy. Given that thousands of bumps could be on a single component, that switch has important implications for environmental audits, because a materials audit can get down to the atomic level.
“If you have a product that contains different materials, and each maybe has one atom of lead, when you aggregate that, at some point that lead becomes measurable and significant,” said Alan Porter, vice president, electronics and semiconductor strategy at Siemens Digital Industries Software.
Currently, there are many bump-and-substrate configurations from a variety of vendors, all with the goal of optimizing electrical connections for better performance. [2] Material advances in underfill, the electrically insulating adhesive layer in the flip chip (not to be confused with “underfilling” [3]) also are increasing efficiencies.
Among the many choices are pure copper “microbumps,” between 20μm and 25μm in diameter, which have the same advantages over larger bumps as bumps have over wire bonding. As pitches got tighter, starting more than a decade ago, many manufacturers began to use “C2 bumps,” a pillar microbump structure that has a tin-silver (SnAg) contact on top.
Those SnAg tips provide reliability benefits. But subtle differences in composition can affect the behavior of bumps. According to Fisher Instruments, “solder bumps with silver content of more than 3% perform better in thermal fatigue testing and are more resistant to shear plastic deformation, while alloys with lower silver content (around 1%) exhibit superior ductility and therefore better fatigue endurance under severe strain conditions.”
One of the basic manufacturing challenges here is keeping materials composition properly balanced. This has created a significant opportunity for X-ray inspection, which sat on the sidelines for years. X-rays can be used to determine material composition, such as the alloy percentage in interconnects or contaminants in a bump. In addition, it can help identify structural defects.
The drawback to X-ray inspection has been speed, and typically it has complemented optical inspection. But as interest grows, there have been significant speed improvements in this technology.
“A bump with a void wouldn’t absorb as much X-ray radiation as the one that’s a solid sphere,” Chen explained. “So we’re looking at the differences and comparing to known-good and known-bad cases to identify defects. Another key application for high-speed X-ray inspection has been to provide die shift and tilt feedback directly to the process tools.”
Process Steps
Current demand for smaller processors, more I/O in smaller footprints, and smaller packages also have led OSATs to re-think the order of processes. “What were once strictly back-end processes, such as packaging, are now being moved more to the front-end,” said John Hoffman, computer vision engineering manager at CyberOptics. “The industry tends to refer to these processes as middle of line, especially when either the fab or packaging house performs the steps.
With the reliability of the final product dependent on precisely aligning the bumps, inspection has to be moved earlier, which compels further adjustments. “Moving measurements further upstream speeds up development iteration cycles,” said Chen. “So there’s significant advantage for inspection immediately after the die-attach process.”
Others agree. “Today in backend/package inspection, we don’t have well-established correlations between inspection and the assembly process,” said Olivier Dupont, product marketing manager in KLA’s ICOS Division, in a recent interview. “This is an area for future development that needs to be built. And as many observe, advanced packaging growth continues to progress. It has to invest in this kind of development.”
Scaling
With dimensions in chips and packages continuing to shrink, bump technology is being supplanted by hybrid bonding.
Today, the smallest pitch and diameters in production are about 20µm pitch and 10µm diameter. “Some customers are trying to go to hybrid bonding after 20 micron pitch, 10 micron diameter, and some of them to 5 micron diameter, 10 micron pitch, then move to hybrid bonding,” said Woo Young Han, application engineering manager at Onto Innovation. “That’s the limitation of our bumps today. Anything smaller than that will be direct copper-to-copper surface bonding.”
One area of concern is the wafer edge. “A few nanometer surface roll-off can ruin the wafer-to-wafer hybrid bonding,” said Han. “A lot of our customers want to do inspection on incomplete dies on the wafer edge. Although it’s not going to be used, any defects on a partial die can ruin the entire process. As a result, a lot of inspection companies are looking at deep learning or AI-based methods to inspect partial dies.”
While those issues are often top-of-mind, there’s another less-well known one during the fabrication of micropillar bumps, according to Jean Trewhella, director of post-fab at GlobalFoundries. “Fabricating the micropillars is not really the biggest challenge,” she said. “Instead, it’s when you try to either test them or connect them to something else, without getting any additional foreign material. It’s not the same kind of cleanroom where we’re doing the bumping.”
In addition, testing itself can sometimes cause damage. “We have to physically touch that bump or ball, and so we have to make sure the Pogo pin technology we’re using is not too destructive,” said Amkor’s Harris. “Also, we have to make sure our environment is clean. If you have a connection between a ball and the power that is dirty, you’ll typically want to increase the voltage or current to meet a certain level while you’re testing. There’s a resistance in that path. And if that’s a carbon-type material, it could burn and damage the socket, damaging the device.”
Conclusion
Amkor’s Scott is optimistic these issues can be resolved. “With decreased bump pitches, new photoresist materials and exposure equipment is needed,” he said. “We’ll need continued investment in better equipment and materials, as well as increased statistical process controls and metrology. Also, it is very important to understand end application requirements to ensure design is appropriate to meet lifetime requirements.”
He’s not alone in that optimism. “Given the number of pillars and everything else, when you stack all of those probabilities together, PPMs aren’t rare anymore,” said John Carulli, GlobalFoundries fellow in the company’s Post Fab Test Development Center. “These are the questions when I benchmark and talk to our various counterparts across the supply chain. There aren’t a lot of solutions at the moment. But a lot of smart people are doing a lot of good work trying to figure it out.”
And there are potentially huge benefits and opportunities to solving these issues. “Higher volume means lower costs, more consistent equipment doing the same thing time in/time out, so costs should come down,” said Chip Greely, vice president of engineering at Promex Industries.
References
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