Balancing Power And Test


The International Test Conference will be held at the Disneyland resort hotel in Anaheim, Calif., from Nov. 4-9. One of the biggest concerns for the test engineering community is to account for the impact on test quality due to additional power management techniques implemented in deep submicron designs. Elaborate power management strategies, such as voltage scaling, clock gating or power-ga... » read more

iPhone 5 – Verizon has a hit!


By Cary Chin My iPhone 5 was delivered to my door as promised on Sept. 21. The UPS guy had a truck full of them, and seemed quite happy to be getting so much attention as he was making his rounds. As with every other iPhone, I carefully unboxed it with some anticipation, but somehow I felt like there was less excitement this time around. After 5 years of iPhone mania, was the luster starti... » read more

Your Job is Harder Than Mine


What I do for a living is listen – a lot – and try to make sense of the myriad challenges that I hear about in terms of design and managing power and performance. What you do as an architect, design engineer or verification engineer is live in the trenches with it all, every day. I admire and respect that. This is especially true as I recently pondered and talked with industry luminaries... » read more

Signal Integrity’s Growing Complexity


By Matt Elmore While in the market for a memory upgrade recently, I was surprised by the availability of commercial DDR memories. You can get 8GB of DDR3 memory, transferring 17GB/s, relatively inexpensively. The progress in memory design is outstanding. From smartphones to gaming PCs, quick communication between the IC and off-chip memory is key to enabling the performance we demand in the... » read more

Improving Reliability


By Dina Medhat Advanced IC designs implement complex strategies to minimize static and dynamic power. Mixed-signal designs typically require different supply voltages for the analog and digital portions of the design, and even all-digital ICs can have many power domains and operating voltages. Typically, some signal lines cross from one domain to another and special interfaces and “voltage p... » read more

LP Test Strategies


By Luke Lang Power during test is one area that is often overlooked. In the worst (but easiest to diagnose) case, excessive test power can lead to a smoking chip on the tester. (You don’t need an engineering education to see the problem.) In a better (but more difficult to diagnose) case, excessive test power will cause reduced yield. Let’s look at what causes excessive test power and how ... » read more

Tales From The Road


By Mike Gianfagna We recently held a SpyGlass Power “boot camp” at Atrenta San Jose. We brought in 15 of our best and brightest field AEs from all over the world and discussed the very latest techniques for advanced power optimization. When you get a group of folks like this together in one room, the learning typically goes both ways. The “students” (the FAEs) certainly learn a lot ... » read more

Near-Threshold Computing


By Bhanu Kapoor There were two main contributing factors to power becoming a big problem ("The Power Wall") starting around the 65nm process technology. First, the fast-growing leakage component became as significant as the dynamic power. Second, the scaling of the supply voltage stopped around 1.1 volts. Process technology advances such as HKMG and 3D tri-gate transistors have enabled con... » read more

Modeling the Future


Every once in a while I read through the employment listings as part of the Semiconductor Manufacturing group on LinkedIn because I find it fascinating to see what employers are looking for even if I am not applying. Particularly for verification engineering position, one of the job responsibilities typically includes development of the architecture for a functional verification environment ... » read more

IBM’s Power7+ Processor


By Barry Pangrle Hot Chips 24 was held Aug. 27-29 with tutorials on the first day and 30-minute technical presentations plus keynote addresses on the second and third days. There were a lot of great presentations and Hot Chips is definitely one of my favorite conferences. So out of all of the presentations, why did I choose IBM’s Scott Taylor’s on Power7+? Well, it’s likely that I’l... » read more

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