category: Blogs – LPHP

category: Auto, Security & Edge AI

The Pain of UPF/CPF
By Ann Mutschler - 10 Feb, 2011 - Comments: 0

Without entering into a debate on the merits of the UPF and CPF, there is a very real and valid concern that designers have today regarding these power intent formats. According to Krishna Balachandran, director of product marketing for low-power verification products at Synopsys, design teams are questioning the validity/correctness of the resulting code. Because they are learning these ... » read more

CES—The Morning After
By Bernard Murphy - 27 Jan, 2011 - Comments: 0

CES 2010 was quite a party, coming off the misery of 2008-2009. Tablets were everywhere, smart phones are racing ahead, the PC is dead. Our industry is reinventing the electronic experience yet again. I saw one forecast of a $1 trillion consumer electronics market within a few years. This is heady stuff. It restores hope not only in the future of electronics but also the possibility that electr... » read more

Power Next
By Barry Pangrle - 13 Jan, 2011 - Comments: 0

Development teams are faced with many tradeoffs when defining a new product: How much should it cost? What functionality or features need to be included? And what level of performance is required? As an example, in order to reduce costs it’s possible to trade away performance by implementing functionality in software instead of in application-specific hardware. For an SoC that already inc... » read more

Golden Power Intent
By Luke Lang - 13 Jan, 2011 - Comments: 0

By Luke Lang A few months ago, I wrote about the rapid adoption of the power intent file for low-power designs. While this is certainly a step in the right direction, some design teams may be taking several steps backwards by not treating the power intent file with the proper respect. For example, I have seen one case where the verification, synthesis, and backend implementation teams each had... » read more

The Challenge Of Packaging
By Ann Mutschler - 13 Jan, 2011 - Comments: 0

Semiconductor packaging isn’t a sexy subject, and it’s one that’s been largely overlooked by the design community. Until now, that is. I recently spoke with Brad Griffin at Cadence, who stressed that managing the power through packages even on a single die is still one of the most challenging things engineers must navigate. “As people integrate more technology into a single chip o... » read more

What is CPS?
By Matt Elmore - 12 Jan, 2011 - Comments: 0

CPS stands for Chip-Package-System. It represents a paradigm shift from the old partitioned approach of IC design into a cohesive methodology that considers the ecology of the system as comprised of the chip, package and board. Today’s design requirements are calling for a revisit to the way we look at IC design and validation. Companies no longer can afford to view design with a silo-base... » read more

Reaching The Breaking Point
By Ron Craig - 16 Dec, 2010 - Comments: 0

By Ron Craig Atrenta recently conducted a user survey on timing constraints, in an effort to find out more about how they are being managed and where the issues are. I expected a diverse range of feedback on different use models, roadblocks etc., but it was very interesting to see some trends pop up: 94% of respondents said that timing constraints were a problem. About 30% of respondents... » read more

Power On
By Barry Pangrle - 02 Dec, 2010 - Comments: 0

By Barry Pangrle Process development is more challenging at each successive technology node but the march forward, for the time being, continues unabated. Voltage scaling stopped around the 100nm node at roughly 1.0v as threshold voltages stopped shrinking in an attempt to keep leakage in check. It’s been the progression to the newer and smaller technology nodes that has really pushed power ... » read more

What’s Your Toggle Rate?
By Luke Lang - 02 Dec, 2010 - Comments: 0

By Luke Lang Now that power is a key specification, designers are looking into various design techniques to reduce power. One thing that designers realize very quickly is that there is a cost associated with these low-power techniques. Some of these costs are silicon area and design complexity. Very quickly, designers face the tradeoff of cost vs. power saving. In order to analyze this tradeof... » read more

Getting Real About Power Management Verification
By Bhanu Kapoor - 02 Dec, 2010 - Comments: 0

By Bhanu Kapoor SoCs that are used in consumer electronics utilize power management techniques that require control of voltage sources. We have discussed the need for power-aware simulation for verification purposes in the past. EDA tools have advanced to include power-aware simulation such as those found with simulators like VCS from Synopsys. In this article, we discuss the need for modeling... » read more

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