category: Blogs – LPHP

category: Auto, Security & Edge AI

AI Warnings For Safer Driving
By Kazuki Ohta - 10 Oct, 2019 - Comments: 0

You’re driving to work, the same route you take every day. But this time, a storm passes over: you’re suddenly faced with heavy rain and reduced visibility. All of a sudden, the “accident score” meter on your car’s dashboard moves into the red. You ease off the gas, move out of the passing lane and your score drops down to amber—you can’t get it into the green due to the advers... » read more

Driving With Chiplets
By Andy Heinig - 24 Sep, 2019 - Comments: 0

The first examples of the upper class of vehicles that can drive autonomously on the highway already have arrived on the market or will be introduced to the market in the coming years. Travel on the highway was selected as the first application because the number of objects that have to be taken into account in front of, next to, and behind the vehicle is manageable. This means the required ... » read more

Scan Compression Is No Longer About Compression
By Rohit Kapur - 16 Sep, 2019 - Comments: 0

Scan compression was introduced in the year 2000 and has seen rapid adoption. Nearly every design’s test methodology today implements this technology, which inserts compression logic in the scan path between the scan I/Os and the internal chains. In this article, we take a critical look at the technology to understand how scan compression has matured. The road to scan compression Since th... » read more

Breaking Down The AI Memory Wall
By Steven Woo - 12 Sep, 2019 - Comments: 0

Over the past few decades, the semiconductor industry has witnessed the rapid evolution of memory technology as new memories helped to usher in new usage models that characterized each decade. For example, synchronous memory helped drive the personal computer (PC) revolution in the 1990s, and this was quickly followed by specialized graphics memory (GPUs) for game consoles in the 2000s. When sm... » read more

High-Performance DSP And Control Processing For Complex 5G Requirements
By Graham Wilson - 12 Sep, 2019 - Comments: 0

In the early 2000s, digital signal processors (DSP) were simple in architecture and limited in performance, but complex in programming. However, they evolved to meet of the increased performance requirements of 3G cellular baseband modem applications. A typical 3G modem system would have a single DSP optimized for dual/quad SIMD MAC performance with basic DSP filter instructions like Fast Fouri... » read more

Simplifying Ultra-Low Power System Design
By Paul Hill - 12 Sep, 2019 - Comments: 0

By Paul Hill and Gordon MacNee With any low-power design, the designer has the choice between choosing low-power components or switching off the power to peripheral devices. When considering the choice of non-volatile flash memories, the designer has these same two options available to them – each of which has its pros and cons from system operation, power consumption and reliability persp... » read more

Place And Route Made Easier And Faster
By Mentor, a Siemens Business - 12 Sep, 2019 - Comments: 0

By Allan Crone A predictable trend in IC design is the ever-increasing size and complexity of designs while keeping the time allocated for the projects the same or shorter. Along with the tape-out pressure, organizations need to find cost savings everywhere possible. Lowering the overall cost of ownership of EDA tools is a viable way to manage the design budget. Consequently, design teams ar... » read more

OIF Eyes Expanded Electrical Link Definitions For 112 Gbps
By Saman Sadr - 12 Aug, 2019 - Comments: 0

The insatiable demand for more bandwidth, lower latencies, and higher speeds is driven by a diverse range of applications and use cases. These include artificial intelligence /machine learning, sophisticated ADAS systems for semi-autonomous vehicles, 4K-8K video streaming, eSports, and AR/VR. With global IP traffic now measured in zettabytes (ZB) per year, hyperscalers and service providers ... » read more

Writing Reusable UPF For RTL And Gate-Level Low Power Verification
By Durgesh Prasad - 08 Aug, 2019 - Comments: 0

By Durgesh Prasad, Jitesh Bansal and Madhur Bhargava The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, and finally during place and route. A major problem is that the UPF needs to be refined or modified at every stage to keep it compatible ... » read more

Getting To Tape-Out Quicker With Analog Layout Generators
By Benjamin Prautsch - 08 Aug, 2019 - Comments: 0

All design engineers know it well: there is hardly any time left until tape-out, but the amount of work that remains is not decreasing as fast as the deadline is approaching. The intricate schematic must still be implemented as a layout, and many recurring tasks slow down the progress. The real crux often lies in specific parts of the circuit – parts that often have lower performance demands ... » read more

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