category: Test, Measurement and Analytics

category: Auto, Security & Edge AI

Solving The Design And Verification Challenges Of High Density Advanced Packaging
By Mentor, a Siemens Business - 07 Aug, 2017 - Comments: 0

This paper discusses ways in which design teams can apply silicon (IC) type processes to the design and verification of the emerging HDAP packages. High Density Advanced Packaging, or HDAP, is the next-generation architecture for increased functional density, higher performance, lower power, smaller PCB footprints, and thinner profiles. This new “breed” of disruptive packaging technology... » read more

5G Test Equipment Race Begins
By Jeff Dorsch - 12 Jul, 2017 - Comments: 0

Test and measurement vendors stand ready to help with the development and deployment of 5G wireless communications, as the technology is fine-tuned and tested in trials around the world. Juniper Research forecasts 5G operator-billed service revenues will rise to $269 billion by 2025, compared with $851 million in 2019, for a compound annual growth rate of 161% during the first seven years of... » read more

Re-Using IP In Packaging
By Ed Sperling - 10 Jul, 2017 - Comments: 0

For the past decade, the promise held forth by advanced packaging was that it would allow chipmakers to mix and match analog and digital IP without worrying about the process node at which they were developed or the physical interactions between components. This is a big deal when it comes to analog. Analog IP doesn't benefit from node shrinking the way digital logic does, and in many cases ... » read more

28nm Chip-Package Interactions In Large eWLB FO-WLP
By STATS ChipPAC - 10 Jul, 2017 - Comments: 0

To meet the continued demand for form factor reduction and functional integration of electronic devices, Wafer Level Packaging (WLP) is an attractive packaging solution with many advantages in comparison with standard Ball Grid Array (BGA) packages. The advancement of fan-out WLP has made it a more promising solution as compared with fan-in WLP, because it can offer greater flexibility in enabl... » read more

Advanced Packaging Picks Up Steam
By Jeff Dorsch - 10 Jul, 2017 - Comments: 0

The semiconductor industry’s push toward continued miniaturization and increasing complexity is driving wider adoption of system-in-package (SiP) technology. One of the big benefits of [getkc id="199" kc_name="SiP"] is that it allows more features to be squeezed into ever-smaller form factors, such as wearable gadgets and medical implants. So while the individual chips in this package may ... » read more

Are All Known Good Tested Devices Created Equal?
By Guy Cortez - 10 Jul, 2017 - Comments: 0

Your known good parts all had passed their required wafer sort, final test, and system-level tests and were shipped to your customers. However, as we all know, a known good part or device sometimes does not stay good and may end up failing prematurely in the field and flagged as an RMA (return material authorization) by your customer. But why is it that some good parts fail early and others las... » read more

Tracking Down Errors With Data
By Ed Sperling - 10 Jul, 2017 - Comments: 0

Michael Schuldenfrei, CTO at [getentity id="22929" comment="Optimal+"], sat down with Semiconductor Engineering to discuss how data will be used and secured in the future, the accuracy of that data, and what impact it can have on manufacturing. What follows are excerpts of that conversation. SE: Can data be shared across the supply chain? Schuldenfrei: We believe it has to happen. If it d... » read more

Test at “West”
By Jeff Dorsch - 10 Jul, 2017 - Comments: 0

As you wander through the North Hall of Moscone Center this week, you may notice that some of the big names in automated test equipment are not on the SEMICON West show floor this year. Advantest America has a booth, but the same cannot be said of Teradyne or Xcerra. Some of the bigger names in test and measurement instruments won’t be found exhibiting at SEMICON West, either – such as Keys... » read more

Get To Market Fast And First With Reusable Circuit Blocks
By Mentor, a Siemens Business - 10 Jul, 2017 - Comments: 0

Reusable circuit blocks enable design teams to build new products quickly, but how do you manage a process that spans both library and design? How do you know which elements need to be managed? This paper describes techniques for leveraging certified circuits and providing continuous circuit improvement, best practices for using reusable circuit blocks, and how these blocks can be used to track... » read more

Challenges For Future Fan-Outs
By Mark LaPedus - 07 Jul, 2017 - Comments: 1

The fan-out wafer-level packaging market is heating up. At the high end, for example, several packaging houses are developing new fan-out packages that could reach a new milestone and hit or break the magic 1µm line/space barrier. But the technology presents some challenges, as it may require more expensive process flows and equipment like lithography. Fig. 1: Redistribution layers. Source: L... » read more

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