category: System-Level Design

category: Auto, Security & Edge AI

Optimize Physical Verification Cost Of Ownership
By Manoz Palaparthi - 29 Jul, 2021 - Comments: 0

As semiconductor designs continue to grow in size and complexity, they put increasing pressure on every stage of the design process. Physical verification, often on the critical path to tape-out, is especially affected. Design rule checking (DRC), layout versus schematic (LVS), and other physical verification runs take longer as chip size increases. In addition, finer geometries introduce new c... » read more

Continuous Education For Engineers
By Brian Bailey - 29 Jul, 2021 - Comments: 0

Continuous education is essential for engineers, but many companies don't recognize the value or they are unwilling to provide the necessary resources. This should be a line of questioning before every new hire makes the decision about where they want to work, because it not only affects their future career, but also impacts the value they can provide to that company during the course of the... » read more

Formally Verifying SystemC/C++ Designs
By Rob van Blommestein - 29 Jul, 2021 - Comments: 0

We’re seeing an increase in the number of designs employing SystemC/C++. This isn’t surprising given the fact that specific use models have emerged to drive common design flows across engineering teams leading to the adoption of high-level synthesis (HLS) at many large semiconductor and electronic systems companies. These HLS tools are a popular method to rapidly generate design components ... » read more

Is RISC-V The Future?
By Roddy Urquhart - 29 Jul, 2021 - Comments: 4

Is RISC-V the future? This is a question that we often get asked, and let’s assume that we mean ‘is RISC-V going to be the dominant ISA in the processor market?’ This is certainly an unfolding situation and has changed significantly in the last five years. RISC-V originated at the University of California, Berkeley, in 2010 and took a number of years to get traction with industry. A bi... » read more

Developing A Real-Time SDR System
By Mariusz Grabowski - 29 Jul, 2021 - Comments: 0

As telecommunication technologies evolve there is an on-going drive for the development of high-performance systems for radio communications. Part of that evolution involves implementing components in software functions that had traditionally been implemented in hardware. Software-defined radio (SDR) is a prime example. Significant amounts of signal processing have been handed over to the ge... » read more

Tape Out On Time With Demand Signoff DRC In P&R
By Siemens EDA - 28 Jul, 2021 - Comments: 0

Physical characteristics of devices have become progressively more complex even as design companies pack more devices on each die. Combining these characteristics with ever more demanding chip power, performance, and area (PPA) goals not only result in increased resource utilization but also challenge existing tools/flows/techniques. Adding on-demand signoff-quality DRC verification inside P&R ... » read more

Automated Conversion Of Xilinx Vivado Projects To ALINT-PRO
By Aldec - 28 Jul, 2021 - Comments: 0

Aldec's ALINT-PRO design verification solution performs static RTL and design constraints code analysis to uncover critical design issues early in the design cycle. The product helps FPGA developers rise to the challenge of designing large FPGA designs and multiprocessor system on chip devices that include high-capacity and high-performance FPGA hardware. The solution supports running rule c... » read more

Parallel RTL Exploration With Unparalleled Accuracy
By Synopsys - 28 Jul, 2021 - Comments: 0

Increasing chip complexity and restrictive advanced node rules have made it harder for implementation tools to achieve PPA targets and node entitlements via last-mile optimizations. RTL Architect enables designers to "shift-left" and predict the implementation impact of their RTL. RTL designers, SoC integrators, and IP developers have embraced this fast, predictive technology to give them new i... » read more

Blog Review: July 28
By Jesse Allen - 28 Jul, 2021 - Comments: 0

Synopsys' Chris Clark considers potential vulnerabilities in automotive over-the-air updates and best practices and new standards the industry can implement to improve security of vehicle software updates. Cadence's Paul McLellan gets a look at expected new fab construction in the coming years and where capacity is being focused. Siemens' Robin Bornoff dives into electromagnetic simulatio... » read more

RF To Millimeter-Wave Front-End Component Design Trends For 5G Communications
By Cadence - 28 Jul, 2021 - Comments: 0

This white paper discusses design challenges and solutions related to the "third wave" of communications, presenting several case studies in which the Cadence AWR Design Environment platform has been used to develop products for 5G and beyond. Examples include a multiband active antenna tuner for cellular internet of things (IoT) machine-type communications (mMTC) applications, a linear power a... » read more

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