category: System-Level Design

category: Auto, Security & Edge AI

Whatever Happened To High-Level Synthesis?
By Brian Bailey - 26 Apr, 2017 - Comments: 0

A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology. It was to be the heart of a new Electronic System Level (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high level design and verificati... » read more

Massive SoC Designs Open Doors To New Era In Simulation
By Cadence - 26 Apr, 2017 - Comments: 0

As system-on-chip (SoC) designs have grown in size, simulation technologies have had to evolve dramatically to keep pace. We’re now at an inflection point where both speed and capacity are essential and new simulation technologies are needed to meet the demands. In this paper, we’ll discuss how simulation has evolved and examine how new technologies such as the Cadence RocketSim Parallel Si... » read more

Blog Review: April 26
By Jesse Allen - 26 Apr, 2017 - Comments: 0

Cadence's Paul McLellan provides an introduction to single-event effects and the challenges created when high-energy neutrons bombard chips. Synopsys' Robert Vamosi looks at the strange turf war between two worms battling for control of IoT security cameras. Mentor's Ayan Pahwa contends that it's the duty of IoT device developers to take security as paramount factor and provide good secur... » read more

Prototyping ARM Cortex-A Processors Using FPGA Platforms
By Arm - 26 Apr, 2017 - Comments: 0

With the increasing cost and complexity involved in new SoC (System-on-Chip) designs, FPGA (Field Programmable Gate Array) prototyping is becoming an increasingly important, or even crucial, part of new SoC projects. By offering a way to get to hardware sooner, FPGA prototyping allows hardware verification and software work to begin earlier, before first silicon, effectively pipelining the desi... » read more

System Bits: April 25
By Ann Mutschler - 25 Apr, 2017 - Comments: 0

Graphene used as copy machine for cheaper semiconductor wafers MIT researchers reminded that in 2016, annual global semiconductor sales reached their highest-ever point, at $339 billion worldwide while in that same year the semiconductor industry spent about $7.2 billion worldwide on wafers. Now, a technique developed by MIT engineers may vastly reduce the overall cost of that wafer technology... » read more

The Week In Review: Design
By Jesse Allen - 21 Apr, 2017 - Comments: 0

Tools Mentor unveiled new formal-based technologies in the Questa Verification Solution. It offers formal-based RTL-to-RTL equivalence checking flows optimized for verification of manual low-power clock gating, bug fix and ECO validation, and ISO 26262 safety mechanism verification, which the company says which can reduce verification turnaround time by 10X. The app also offers expanded cloc... » read more

Supporting CPUs Plus FPGAs (Part 3)
By Brian Bailey - 19 Apr, 2017 - Comments: 0

While it has been possible to pair a CPU and FPGA for quite some time, two things have changed recently. First, the industry has reduced the latency of the connection between them and second, we now appear to have the killer app for this combination. Semiconductor Engineering sat down to discuss these changes and the state of the tool chain to support this combination, with Kent Orthner, system... » read more

Blog Review: April 19
By Jesse Allen - 19 Apr, 2017 - Comments: 0

Mentor's Tom Fitzpatrick explains what the Portable Stimulus standard will do, what it won't, and why the choice of input language defined by the standard matters. Cadence's Paul McLellan listens in as IRDS chairman Paolo Gargini explains how long it takes technology breakthroughs to make out of the lab and into high-volume manufacturing. Synopsys' Robert Vamosi points to the recent sound... » read more

System Bits: April 18
By Ann Mutschler - 18 Apr, 2017 - Comments: 0

RISC-V errors Princeton University researchers have discovered a series of errors in the RISC-V instruction specification that now are leading to changes in the new system, which seeks to facilitate open-source design for computer chips. In testing a technique they created for analyzing computer memory use, the team found over 100 errors involving incorrect orderings in the storage and retr... » read more

The Week In Review: Design
By Jesse Allen - 14 Apr, 2017 - Comments: 0

M&A Synapse Design acquired Asilicon, a design services firm based in Ranchi Jharkhand, India. Through the acquisition, Synapse Design adds a second design center in India and gains an additional 80 engineers. "The focus of the Ranchi office will be to provide lower-cost offshore design center services for our customer's designs targeting 7- and 10-nm process technology," said Satish Bag... » read more

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