category: System-Level Design

category: Auto, Security & Edge AI

U.V.M. Spells Relief
By Henry Chan - 22 Dec, 2015 - Comments: 0

Verification can be a challenging endeavor. As designs grow in size and complexity, engineers are having difficulty confirming their designs behave properly. This is where UVM may provide some relief. UVM aims to deliver an easier and more flexible way of creating robust test environments so that you can verify those difficult designs effortlessly. So what is UVM? UVM is a verification meth... » read more

Reflections On 2015
By Brian Bailey - 22 Dec, 2015 - Comments: 0

It is easy to make predictions, but few people can make them with any degree of accuracy. Most of the time, those predictions are forgotten by the end of the year and there is no one to do a tally of who holds more credibility for next year. Not so with SemiEngineering. We like to hold people's feet to the fire, but while the Pants-On-Fire meter may be applicable to politicians, we like to thin... » read more

Developing Effective Design Strategies for Today’s Wearable Devices: Power Management
By Mentor, a Siemens Business - 21 Dec, 2015 - Comments: 0

As the next wave of wearable devices expands into a new class of revolutionary and innovative products, there will be a growing importance placed on the real-time operating system (RTOS) and corresponding middleware. Wearable System-on-Chip (SoC) processors require an operating system optimized for size and performance with power-efficient wireless connectivity options needed for machine-to-mac... » read more

Scaling Automated Software Testing With Virtualizer Development Kits
By Synopsys - 21 Dec, 2015 - Comments: 0

In this whitepaper we will discuss how simulation-based Virtualizer Development Kits (VDKs) enable software to be tested in a system context much earlier, bridging the gap with unit and integration testing. Moreover, we will discuss how VDKs offer a more scalable solution as they consist of simulation models and hence alleviate the dependency on hardware labs. To read more, click here. » read more

C-Based SoC Design Flow And EDA Tools
By Aldec - 21 Dec, 2015 - Comments: 0

This paper examines the achievements and future of SoC design methodology and design flow from the viewpoints of an in- house EDA team of an ASIC and system vendor. We initially discuss the problems of the design productivity gap caused by the SoC’s complexity and the timing closure caused by deep submicron technology. To solve these two problems, we propose a C-based SoC design environment t... » read more

Who’s Profiting From Complexity
By Ed Sperling - 21 Dec, 2015 - Comments: 0

Tool vendors' profits increasingly are coming from segments that performed relatively poorly in the past, reflecting both a rise in complexity in designing chips and big improvements in the tools themselves. The impacts of power, memory congestion, advanced-node effects such as process variation, [getkc id="160" kc_name="electromigration"] and RC delay in [getkc id="36" kc_name="interconnect... » read more

The Week In Review: Design/IoT
By Jesse Allen - 18 Dec, 2015 - Comments: 0

Tools, IP, & IoT Mentor Graphics updated its general purpose computational fluid dynamics product, adding improved mesh handling, an enhanced transient solver, a robust EDA interface, and an interface to Abaqus Finite Element Analysis (FEA) software for stress analysis. Arasan uncorked MIPI DSI v1.3 controller IP with support for Display Stream Compression, Sub links, Deskew, and Chec... » read more

Blog Review: Dec. 16
By Jesse Allen - 16 Dec, 2015 - Comments: 0

Power from nuclear fusion just made the leap from sci-fi to the real world in this week's top five engineering tech picks by Ansys' Bill Vandermark. Plus, stacking chips tall, helping gunshot victims survive, and a shoe just for you. A world without paralysis? Rambus' Aharon Etengoff takes a look at one research group's latest advancement, a brain implant that allowed a paralyzed man to bypa... » read more

System Bits: Dec. 15
By Ann Mutschler - 15 Dec, 2015 - Comments: 0

Building chips skyscraper style With the aim of boosting electronic performance by factor of a thousand, a team of researchers led by Stanford University engineers have created a skyscraper-like chip design, based on materials more advanced than silicon. For many years, computer systems have been designed with processors and memory chips laid out like single-story structures in a suburb whe... » read more

The Week In Review: Design/IoT
By Jesse Allen - 11 Dec, 2015 - Comments: 0

Mergers & Acquisitions Zuken acquired one of its USA resellers, electrical applications provider Caetek. The company also developed software for harness manufacturers that integrated with Zuken's electrical wiring, control systems and fluid engineering toolset. The NXP-Freescale merger is, at last, official. The largest revenue source for the combined company will be automotive, proje... » read more

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