category: System-Level Design

category: Auto, Security & Edge AI

Why Implementation Matters To System Design And Software
By Frank Schirrmeister - 27 Aug, 2015 - Comments: 0

There has been quite some discussion in the recent past how well abstraction really works in enabling system design and verification. As I admitted in “Confessions of an ESL-Aholic” a while back, I have revised my view significantly over the years. While thinking originally of abstraction more as an panacea, it turns out that important decisions and analyses, such as for power and performan... » read more

Hardware-Software Co-Design
By Tom De Schutter - 27 Aug, 2015 - Comments: 1

A famous electronics company recently launched a new TV and web commercial emphasizing the importance of designing hardware and software together. (You can view the video here.) It is interesting to see that we have evolved to a state where a phone maker actually feels compelled to talk about the technical details of how the phone was designed. Rather than focusing on the screen resolution,... » read more

As Moore’s Law Slows, Hedge Your Bets With Design Process Efficiency
By Kurt Shuler - 27 Aug, 2015 - Comments: 0

Are you dreading the day when Moore’s Law comes to a grinding halt? I’m concerned, but I’m not as fatalistic as some. Here's why: There are plenty of ways to eke out more scalability in the semiconductor design process through greater efficiency. SoC design realities make it imperative to re-evaluate mature semiconductor processes for greater efficiencies that yield lower costs, higher... » read more

What Happened To ESL
By Ann Mutschler - 27 Aug, 2015 - Comments: 3

Electronic system level ([getkc id="48" kc_name="ESL"]) is a design methodology idea that gained steam in the last 20 years centered mainly around the idea of using higher levels of abstraction to define and implement an electronic design. It was defined and promoted by industry analyst Gary Smith, then at Gartner-Dataquest, and so much has been written on this topic over the years that ESL ... » read more

Developing High-Reliability FPGAs For DO-254
By Louie De Luna - 27 Aug, 2015 - Comments: 0

You have been developing FPGAs for a long time, and you know your designs from top to bottom. You know every interface protocol, configuration and optimization. You can visualize your timing diagram like you can visualize your upcoming vacation in Hawaii. You can manually write down your memory mapping accurately while under oath. You can pinpoint all CDC paths and emulate metastability in your... » read more

Full-Flow Tool Suite For Both Custom Analog And Mixed-Signal Designs
By Mentor, a Siemens Business - 26 Aug, 2015 - Comments: 0

The Tanner EDA AMS IC design flow offers a cohesive, integrated mixed-signal design suite that is ideally suited to IoT and project-based design with its extremely short cycle times and sensitivity to cost. Learn more about the Tanner AMS solution in this white paper. To read more, click here. » read more

Introduction To DO-254
By Aldec - 26 Aug, 2015 - Comments: 0

For almost two decades, avionics system manufacturers have only had to adhere to DO-178 for the development of airborne software. RTCA/DO-178A was recognized by the Federal Aviation Administration (FAA) in 1985 for the development of airborne software, but RTCA/DO-254 was only recognized by the FAA in 2005 for the development of airborne electronic hardware (AEH). Developers of AEH are now face... » read more

Gate-Level Simulation Methodology
By Cadence - 26 Aug, 2015 - Comments: 0

The increase in design sizes and the complexity of timing checks at 40nm technology nodes and below is responsible for longer run times, high memory requirements, and the need for a growing set of gate-level simulation (GLS) applications including design for test (DFT) and low- power considerations. As a result, in order to complete the verification requirements on time, it becomes extr... » read more

Blog Review: Aug. 26
By Jesse Allen - 26 Aug, 2015 - Comments: 0

Synopsys' Marc Greenberg attended IDF and learned more about the newly announced Intel/Micron 3D XPoint memory technology named Optane including initial ship dates and some implementation details. In concluding his analysis of the 2014 Functional Verification Study, Mentor's Harry Foster reveals an unexpected finding about design size and respins. How do you keep your power grid from bein... » read more

Five Questions: Jeff Bier
By Brian Bailey - 26 Aug, 2015 - Comments: 0

Jeff Bier, founder and president of BDTI, sat down with Semiconductor Engineering to discuss the creation of the Embedded Vision Alliance and the proliferation of neural network technology into embedded systems. SE: Why was the Embedded Vision Alliance formed? Bier: About 5 years ago, computer vision was on the verge of becoming a world changing technology. It was becoming possible, for t... » read more

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